Microprocessor self-test apparatus and method
AssigneeAllen-Bradley Company, Inc.
InventorKenneth William Batcher
Life of this patent
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Abstract
A method and apparatus for testing a digital integrated circuit (IC) for faults wherein the IC includes a memory, a microprocessor, an operand register, and a random data generator which is responsive to integrated circuit data indicative of the instantaneous IC state. A short test code including operational code instructions in the memory is performed by the microprocessor which manipulates data in the operand register. Periodically, the random data generator provides seed data to the microprocessor which changes the test code in a random manner and modifies the data stored in the operand register. At the end of a prescribed number of passes through the test code, the data generator produces an IC signature which can be compared to a known correct signature to identify IC faults.
Claims23
A method of testing a digital integrated circuit for faults, the integrated circuit having access to a memory for storing a test code including a plurality of separate instructions and a known correct IC signature, a microprocessor for performing the test code, an operand register having a plurality of register slots for storing operands manipulated by the microprocessor according to the test code, a data bus for transferring bus data to and from the register slots and the memory, and a random data generator including a signature register storing a signature word, the method comprising the steps of:
- a) supplying each register slot with initial register data and the signature register with an initial signature word;
- b) performing the test code and, while performing the test code, periodically combining the signature word and said bus data to provide a modified signature word;
- c) after performing the test code, altering the test code as a function of the modified signature word to provide a modified test code as the test code;
- d) repeating steps b) and c) for a predetermined number of passes through the test code;
- e) after said predetermined number of passes, comparing the signature word to the known correct IC signature;
- and
- f) where the signature word is not identical to the known correct IC signature, signaling a faulty integrated circuit.
An apparatus for testing a digital integrated circuit on a chip for faults, the apparatus including cooperating on circuit hardware and software, the apparatus comprising:
- a microprocessor having access to a memory, the memory for storing a test code, including a plurality of instructions and a known correct IC signature, the instructions including a variable code portion, the microprocessor for performing said instructions;
- operand registers for storing data which is manipulated by the microprocessor according to the test code;
- a data bus for transferring bus data between the memory, microprocessor, and operand register;
- a random data generator including a signature register for storing a signature word, the generator connected to the bus for observing bus data, the generator periodically combining bus data and the signature word to provide a new signature word, the new data signature word being changed each time the generator combines;
- whereby, after the microprocessor performs the variable code portion, the microprocessor uses an instantaneous new signature word as random seed data to modify the variable code portion producing a modified variable code portion, and then performs the modified variable code portion, and, after modifying and performing the variable code portion a predetermined number of times, the microprocessor compares the instantaneous new signature word to the known correct signature word, thereafter indicating a faulty circuit when the instantaneous new signature and known correct signature words are not identical.
Dependencies are inferred from the claim text.