Signal processing apparatus and method

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter that samples an input signal at sampling intervals and has an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an adaptive equalizer coupled to said filter;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit;
• wherein a plurality of said data packets are grouped in frames, each said frame further comprising a frame header, and a training sequence in said frame header;
• wherein said equalizer further comprises:
• a first response filter;
• a circuit for adjusting coefficients of said first response filter, said circuit being, responsive to an error signal that is derived from a difference between an output of said first response filter and said training sequence, wherein said circuit comprises means for executing a least-mean-square algorithm;
• a phase tracking circuit for producing an in-phase component and a quadrature component that is representative of said modulated signal in accordance with the formula
• data=a(t) cos .phi.+a(t) sin .phi.
• wherein
• data is an output
• .phi. is phase error;
• a(t) is transmitted data;
• a(t) is the quadrature component of a(t);
• wherein an output of said phase tracking circuit is in accordance with the formula
• output.sub.c =a(t) (cos .theta. cos .phi.+sin .theta. sin .phi.)+a(t) (sin .phi. cos .theta.-cos .phi. sin .theta.)
• wherein .theta. is an angle of rotation of a signal constellation of said modulated signal, said phase tracking circuit comprising;
• a second response filter;
• and
• circuit means including said second response filter for estimating said angle .theta. according to said least-mean-square algorithm.

A method of signal processing received data packets that are transmitted through a channel, wherein the data packets include information data and error correction data for correcting errors in the received data, and said packets are represented in a modulated signal having pretransmission characteristics, and are demodulated following transmission, and said data packets are grouped in frames, each frame comprising a frame header having a synchronization sequence and a training sequence, the method comprising the steps of:

• detecting said synchronization sequence;
• sampling an input signal at sampling intervals following transmission of said input signal through a channel;
• while said step of sampling is being performed adjusting a frequency and a phase of said sampling intervals;
• determining that said step of adjusting a frequency and a phase of said sampling intervals has been completed within a first predetermined tolerance;
• while said step of sampling is being performed adjusting a frequency and a phase of said input signal, and providing an error signal that is indicative of a magnitude of said input signal and a reference magnitude;
• determining that said step of adjusting a frequency and a phase of said input signal has been completed within a second predetermined tolerance;
• determining that said step of providing an error signal has been completed within a third predetermined tolerance;
• filtering said sampled input signal to conform a post-sampling characteristic thereof to a pretransmission characteristic thereof;
• adaptively equalizing said filtered input signal in accordance with predetermined information encoded in said modulated signal to conform said filtered input signal to characteristics of said channel wherein said step of adaptively equalizing is performed using a reference, and further comprises the steps of producing an in-phase component and a quadrature component that is representative of said modulated signal in accordance with the formula
• data=a(t) cos .phi.+a(t) sin .phi.
• wherein data is an output
• .phi. is phase error;
• a(t) is transmitted data;
• a(t) is the quadrature component of a(t);
• wherein a result is in accordance with the formula
• output.sub.c =a(t) (cos .theta. cos .phi.+sin .theta. sin .phi.)+a(t) (sin .phi. cos .theta.-cos .phi. sin .theta.)
• wherein .theta. is an angle of rotation of a signal constellation of said modulated signal;
• adapting .theta. in accordance with a least-mean-square algorithm to yield a derotated signal constellation;
• submitting said adaptively equalized input signal to an error correcting circuit to produce corrected data;
• and
• outputting said corrected data;
• wherein said step of adjusting a frequency and a phase of said input signal, said step of providing an error signal, said step of filtering said sampled input signal, said step of adaptively equalizing said filtered input signal, and said step of submitting said adaptively equalized input signal to an error correcting circuit are performed using a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter for sampling an input signal at sampling intervals and having an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• an automatic gain control circuit coupled to said ADC output, that provides an error signal that is indicative of a difference between a magnitude of said input signal and a reference magnitude;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an equalizer coupled to said filter, said equalizer having characteristics that are adaptively varied in accordance with predetermined information encoded in said modulated signal, whereby an output of said equalizer conforms to characteristics of said channel;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein blocks of said packets are interleaved at an interleaving depth, the apparatus further comprising a deinterleaving circuit that is incorporated in said integrated circuit, the deinterleaving circuit comprising:
• a random access memory for memorizing said interleaved packets, said random access memory having a capacity that does not exceed a block of interleaved data, and having a plurality of rows and a plurality of columns, wherein said rows define a plurality of groups:
• a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by a stride;
• a second circuit for successively reading and writing data out of and into said random access memory respectively at an address of said random access memory that is determined by said address signal;
• a third circuit for increasing said stride by said interleaving depth, wherein said stride is increased upon deinterleaving of a block of interleaved data;
• and
• a control circuit for operating said second circuit in a selected one of a first operating mode, wherein said random access memory is accepting incoming data and is not producing outgoing data, a second operating mode, wherein said random access memory is accepting incoming data and producing outgoing data, and a third operating mode, wherein said random access memory is not accepting incoming data and is producing outgoing data;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are interleaved in blocks at an interleaving depth, and transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter that samples an input signal at sampling intervals and has an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an adaptive equalizer coupled to said filter;
• an error correcting circuit coupled to said equalizer;
• an output interface, coupled to said error correcting circuit;
• and
• a deinterleaving circuit comprising:
• a random access memory for memorizing said interleaved packets, said random access memory having a capacity that does not exceed a block of interleaved data, and having a plurality of rows and a plurality of columns, wherein said rows define a plurality of groups;
• a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by a stride;
• a second circuit for successively reading and writing data out of and into said random access memory respectively at an address of said random access memory that is determined by said address signal;
• a third circuit for increasing said stride by said interleaving depth, wherein said stride is increased upon deinterleaving of a block of interleaved data;
• and
• a control circuit for operating said second circuit in a selected one of a first operating mode, wherein said random access memory is accepting incoming data and is not producing outgoing data, a second operating mode, wherein said random access memory is accepting incoming data and producing outgoing data, and a third operating mode, wherein said random access memory is not accepting incoming data and is producing outgoing data;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, said deinterleaving circuit, and said output interface comprise a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter that samples an input signal at sampling intervals and has an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an adaptive equalizer coupled to said filter;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein said analog-to-digital converter comprises a comparator having first and second units, each of said units comprising:
• a capacitor connected to a first node and a second node;
• first switch means for connecting said first node to a selected one of an input voltage and a reference voltage;
• an inverter connected to said second node and having an output, wherein said inverter has a small-signal gain between said second node and said output thereof;
• and
• second switch means for connecting said output of said inverter of one of said first and second units to said first node of another of said first and second units, whereby said first and second units are cross-coupled in a positive feed back loop when said second switch means of said first unit and said second switch means of said second units are closed, and said output of said inverter is representative of a comparison of said input voltage and said reference voltage;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter for sampling an input signal at sampling intervals and having an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• an automatic gain control circuit coupled to said ADC output, that provides an error signal that is indicative of a difference between a magnitude of said input signal and a reference magnitude;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an equalizer coupled to said filter, said equalizer having characteristics that are adaptively varied in accordance with predetermined information encoded in said modulated signal;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein a plurality of said data packets are grouped in frames, each said frame further comprising a frame header, and said predetermined information comprises a training sequence in said frame header;
• wherein said equalizer comprises:
• a first response filter;
• a circuit for adjusting coefficients of said first response filter according to a least-mean-square algorithm, said circuit being responsive to an error signal that is derived from a difference between an output of said first response filter and said predetermined information;
• a phase tracking circuit for producing an in-phase component and a quadrature component that is representative of said modulated signal in accordance with the formula
• data=a(t) cos .phi.+a(t) sin .phi.
• wherein
• data is an output
• .phi. is phase error;
• a(t) is transmitted data;
• a(t) is the quadrature component of a(t);
• wherein an output of said phase tracking circuit is in accordance with the formula
• output.sub.c =a(t) (cos .theta. cos .phi.+sin .theta. sin .phi.)+a(t) (sin .phi. cos .theta.-cos .phi. sin .theta.)
• wherein .theta. is an angle of rotation of a signal constellation of said modulated signal, said phase tracking circuit comprising;
• a second response filter;
• and
• circuit means including said second response filter for estimating said angle .theta. according to said least-mean-square algorithm;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital conveyer that samples an input signal at sampling intervals and has an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an adaptive equalizer coupled to said filter;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein said analog-to-digital converter comprises a comparator having first and second units, each of said units comprising:
• a capacitor connected to a first node and a second node;
• first switch means for connecting said first node to a selected one of an input voltage and a reference voltage;
• an inverter connected to said second node and having an output, wherein said inverter has a small-signal gain between said second node and said output thereof;
• and
• second switch means for connecting said output of said inverter of one of said first and second units to said first node of another of said first and second units, whereby said first and second units are cross-coupled in a positive feed back loop when said second switch means of said first unit and said second switch means of said second units are closed, and said output of said inverter is representative of a comparison of said input voltage and said reference voltage;
• wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter that samples an input signal at sampling intervals and has an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an equalizer coupled to said filter;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein said equalizer comprises:
• a phase tracking circuit for producing an in-phase component and a quadrature component that is representative of said modulated signal, said phase tracking circuit comprising;
• a first response filter;
• a second response filter;
• and
• circuit means including said second response filter for estimating an angle of rotation of a signal constellation of said modulated signal according to a least-mean-square algorithm.

A method of signal processing received data packets that are transmitted through a channel, wherein the data packets include information data and error correction data for correcting errors in the received data, and said packets are represented in a modulated signal having pretransmission characteristics, and are demodulated following transmission, and said data packets are grouped in frames, each frame comprising a frame header having a synchronization sequence and a training sequence, the method comprising the steps of:

• detecting said synchronization sequence;
• sampling an input signal at sampling intervals following transmission of said input signal through a channel;
• while said step of sampling is being performed adjusting a frequency and a phase of said sampling intervals;
• determining that said step of adjusting a frequency and a phase of said sampling intervals has been completed within a first predetermined tolerance;
• while said step of sampling is being performed adjusting a frequency and a phase of said input signal, and providing an error signal that is indicative of a magnitude of said input signal and a reference magnitude;
• determining that said step of adjusting a frequency and a phase of said input signal has been completed within a second predetermined tolerance;
• determining that said step of providing an error signal has been completed within a third predetermined tolerance;
• filtering said sampled input signal to conform a post-sampling characteristic thereof to a pretransmission characteristic thereof;
• adaptively equalizing said filtered input signal in accordance with predetermined information encoded in said modulated signal to conform said filtered input signal to characteristics of said channel wherein said step of adaptively equalizing is performed using a reference, and further comprises the steps of producing an in-phase component and a quadrature component that is representative of said modulated signal;
• adapting an angle of rotation of a signal constellation of said modulated signal in accordance with a least-mean-square algorithm to yield a derotater signal constellation;
• submitting said adaptively equalized input signal to an error correcting circuit to produce corrected data;
• and
• outputting said corrected data.

A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising:

• an analog-to-digital converter for sampling an input signal at sampling intervals and having an ADC output;
• a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals;
• a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal;
• an automatic gain control circuit coupled to said ADC output, that provides an error signal that is indicative of a difference between a magnitude of said input signal and a reference magnitude;
• a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal;
• an equalizer coupled to said filter, said equalizer having characteristics that are adaptively varied in accordance with predetermined information encoded in said modulated signal, whereby an output of said equalizer conforms to characteristics of said channel;
• an error correcting circuit coupled to said equalizer;
• and
• an output interface, coupled to said error correcting circuit;
• wherein blocks of said packets are interleaved at an interleaving depth, the apparatus further comprising a deinterleaving circuit that is incorporated in said integrated circuit, the deinterleaving circuit comprising:
• a random access memory for memorizing said interleaved packets, said random access memory having a capacity that does not exceed a block of interleaved data, and having a plurality of rows and a plurality of columns, wherein said rows define a plurality of groups;
• a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by a stride;
• a second circuit for successively reading and writing data out of and into said random access memory respectively at an address of said random access memory that is determined by said address signal;
• and
• a third circuit for increasing said stride by said interleaving depth, wherein said stride is increased upon deinterleaving of a block of interleaved data.