US 5,668,817 A · Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths

Abstract

A self-testable Digital Signal Processing (DSP) integrated circuit is described, using a Built-In Self Test (BIST) scheme suitable for high performance DSP datapaths. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DataPath-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan-based BIST technique is also presented. DP-BIST is used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.

Claims20

Dependent claims

A integrated circuit including a self-testable digital signal processor comprising:

a programmable data path comprising an arithmetic and logic unit (ALU), a register, and a plurality of logic blocks for digital signal processing (DSP) functions comprising non-arithmetic and non-linear functions,
a multiplexor responsive to a test signal for switching the datapath between
a first mode for normal operation of the digital signal processor, and
a second (test) mode for test operation of the digital signal processor wherein the ALU functions as a test pattern generator and a test data compactor, wherein a carry out bit of the ALU is circulated back to the ALU as a carry in bit.

1 more element

A method for built-in-self-testing of an ASIC comprising a digital signal processor characterized by a programmable data path comprising an arithmetic and logic unit (ALU), a register, and a plurality of logic blocks for digital signal processing (DSP) functions comprising non-arithmetic and non-linear functions,

a multiplexor responsive to a test signal for switching the datapath between
a first mode for normal operation of the digital signal processor, and
a second (test) mode for test operation of the digital signal processor wherein the ALU functions as a test pattern generator and a test data compactor, wherein a carry out bit of the ALU is circulated back to the ALU as a carry in bit, the method comprising:
a) initializing the circuit by steps comprising:
applying a test signal to initiate the test mode enabling rotation of a carry out big from ALU as a carry in bit,
initiating generation of test patterns through operation of the ALU as a pseudo random pattern generator;
b) applying said pseudo random test patterns to the datapath of the circuit;
reading the compressed signature of the circuit;
and
c) comparing the compressed signature to a non-faulty signature to determine a fault or no fault condition.

7 more elements

Dependencies are inferred from the claim text.

Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths

Life of this patent

Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths

Life of this patent

Abstract

Claims20