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US 5,668,773 AGranted
Synchronous burst extended data out DRAM
AssigneeMicron Technology, Inc.
InventorsPaul S. Zagar, Troy A. Manning, Todd Merritt
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Abstract
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additioned memory addresses. A clock signed is provided to synchronize the burst operations. The clock signed is independent of an address latch signal used to latch an external address.
Claims2
A memory device comprising:
- a plurality of addressable memory elements;
- and
- addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal,
- wherein the clock signal is provided on an output enable input.
1 more element
A synchronous memory device comprising:
- a memory array having a plurality of addressable memory elements;
- a plurality of address inputs for receiving memory element addresses;
- an address latch input for receiving an address latch signal;
- an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal;
- and
- an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses,
- wherein the clock signal is provided on an output enable input.
4 more elements
Dependencies are inferred from the claim text.