Semiconductor memory device and access method for the same
AssigneeSharp Kabushiki Kaisha
InventorYasuhiro Hotta
Life of this patent
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Abstract
A semiconductor memory device comprising a memory cell array includes a plurality of memory cells. The device includes: a predecoder for dividing a plurality of bits of an address signal into at least two bit strings so as to decode each bit string and output predecoded results of each bit string in parallel; a series of shift registers, each shift register being provided for a respective bit string, receiving the predecoded results of the corresponding bit string as shift data, shifting the received shift data, thereby generating and outputting predecoded signal bits; and a main decoder for decoding the predecoded signal bits output from the plurality of shift registers and selecting a memory cell in the memory cell array in accordance with the results of the decoding.
Claims8
A semiconductor memory device comprising a memory cell array including a plurality of memory cells, the device comprising:
- a predecoder for dividing a plurality of bits of an address signal into at least two bit strings so as to decode each bit string and output predecoded results of each bit string in parallel;
- a series of shift registers, each shift register being provided for a respective bit string, receiving the predecoded results of the corresponding bit string as shift data, shifting the received shift data, thereby generating and outputting predecoded signal bits;
- and
- a main decoder for decoding the predecoded signal bits output from the plurality of shift registers and selecting a memory cell in the memory cell array in accordance with the results of the decoding.
An access method for a semiconductor memory device comprising a memory cell array including a plurality of memory cells, the method comprising the steps of:
- dividing a plurality of bits of an input address signal into at least two bit strings;
- decoding each bit string and generating predecoded results for each bit string;
- latching the predecoded results of the bit strings as shift data, respectively;
- generating predecoded signal bits by circularly shifting the respective shift data;
- and
- decoding the predecoded signal bits so as to select a memory cell in the memory cell array in accordance with results of the decoding.
Dependencies are inferred from the claim text.