US 5,668,769 A · Memory device performance by delayed power-down

Abstract

The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Claims5

Dependent claims

A method of reducing voltage on power busses of an integrated circuit caused by short chip-disable durations, said method comprising:

detecting an external chip-disable pulse occurring before a minimum time duration;
preventing said chip-disable pulse from powering down selected internal DC paths of said integrated circuit;
and
simultaneously, preserving the output-driver high-impedance functionality of the chip-disable signal.

1 more element

A circuit for reducing power consumption in an integrated circuit, said circuit comprising:

a chip-enable buffer having a chip-enable signal input and an output;
an output-disable buffer having a output-disable signal input, a disabling input coupled to said output of said chip-enable buffer, and an output;
at least one address buffer having an address input and a disabling input;
sense amplifiers having a disabling input and having data outputs;
output drivers having a disabling input and having data inputs coupled to said data outputs of said sense amplifiers;
and
a delay circuit having an output and an input;
said input of said delay circuit coupled said output of said chip-enable buffer, said output of said delay circuit coupled to said disabling inputs of said address buffer and said disabling input of said sense amplifiers.

5 more elements

Dependencies are inferred from the claim text.

Memory device performance by delayed power-down

Life of this patent

Memory device performance by delayed power-down

Life of this patent

Abstract

Claims5