Method and apparatus for increasing memory read access speed using double-sensing

A computer system comprising:

• a bus to communicate information
• a processor coupled to the bus to process information;
• and
• a cache memory coupled to the processor to store information, the cache memory including:
• an array of memory cells including a first memory cell to be read,
• a first sense amplifier coupled to the first memory cell and having an output coupled to an input of the processor, the first sense amplifier providing a first indicated data value to the processor at a first sense time,
• a second sense amplifier coupled to the first memory cell, the second sense amplifier providing a second indicated data value on an output at a second, later sense time, and
• a comparator having inputs coupled to the first and second sense amplifier and an output coupled to the processor, the comparator invalidating the first indicated data value provided to the processor and providing the second indicated data value to the processor if the first and second data values are different.

In a computer system, a method for reading data from a memory cell comprising the steps of:

• accessing the memory cell for reading in response to a read request from a processor;
• sensing a value stored in the cell at a first time;
• communicating the value sensed at the first time to the processor;
• sensing the value stored in the cell at a second, later time;
• comparing the value sensed at the first time to the value sensed at the second, later time;
• and
• if the valued sensed at the first time and the value sensed at the second, later time are different, performing the steps of:
• sending a signal to the processor to invalidate the value sensed at the first time, and
• communicating the value sensed at the second time to the processor.