Back to results
US 5,668,764 AGranted
Testability apparatus and method for faster data access and silicon die size reduction
AssigneeTexas Instruments Incorporated
InventorVipul A. Surlekar
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorVipul A. Surlekar
Estimating the term…
In order to minimize the time consuming testing of large (e.g., 4 mega-bit) memory units, the units can be designed with alternate test mechanisms incorporated therein. The design for testability (DFT) techniques used in dynamic random access memories to reduce the time required testing use parallel read/write procedures and similar techniques. The technique of the present invention compares actual data signal output with an expected data signal in parallel resulting in a faster determination of the memory status. The additional apparatus is incorporated in the memory unit in the vicinity of the group of storage cells under test. By appropriate selection of the location and function of the apparatus, the test apparatus can result in a smaller chip size, faster processing operation, and lower power consumption. The DFT technique reduces the time for testing by incorporating parallel read/write procedures along with additional test procedures. Little additional apparatus is required for the implementation of the improved test procedures. The benefit derived from the improved testing techniques exceeds the relatively modest implementation cost.
Testing apparatus for testing the storage and retrieval of an applied data signal in an array of storage cells in an integrated circuit memory unit, wherein said storage cells are arranged in a plurality of storage cell groups, said apparatus comprising:
Testing apparatus for testing the storage and the retrieval of an expected logic signal in an array of storage cells in a integrated circuit memory unit, wherein said storage cells are arranged in a plurality of storage cell groups, said apparatus comprising:
A method of using testing apparatus incorporated in an integrated memory circuit, said method comprising the steps of:
Testing apparatus for an integrated circuit semiconductor unit, said memory cell including a storage cell array arranged in a plurality of storage cell groups, said testing apparatus comprising:
In a semiconductor memory unit in which the memory cell array is divided into a plurality of memory cell groups, said semiconductor memory unit including testing apparatus, said testing apparatus comparing data signals retrieved from storage cells in a plurality of storage cell groups, said storage cells having an applied data signal stored therein, at least part of said testing apparatus performing comparison operations associated with each storage cell group, an improved method of testing stored data signals, said improvement comprising the steps of:
Dependencies are inferred from the claim text.