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US 5,668,757 AGranted
Scalable flash eeprom memory cell and array
OwnerChing-Shi Jenginventor
Life of this patent
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Abstract
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.
Claims23
An electrically erasable and programmable read only memory array, said memory array comprising:
- a semiconductor substrate;
- a plurality of floating gate memory transistors arranged in a matrix of a plurality of rows and a plurality of columns, each memory transistor having four terminals;
- a plurality of first column lines, each first column line connecting a first terminal of all the memory transistors arranged in the same column;
- a plurality of first row lines, each first row line connecting a second terminal of all the memory transistors arranged in the same row;
- a plurality of second row lines, each second row line connecting a third terminal of all the memory transistors arranged in the same row;
- a plurality of third row lines, each third row line connecting a fourth terminal of all the memory transistors arranged in the same row;
- said memory transistors arranged in the same row having the same first, second and third row lines;
- column decoding means for receiving a column address signal and for selecting one of a plurality of first column lines in response thereto;
- and
- row decoding means for receiving a row address signal and for selecting one of a plurality of first, second and third row lines in response thereto.
7 more elements
An electrically erasable and programmable read only memory array, said memory array comprising:
- a semiconductor substrate;
- a plurality of floating gate memory transistors arranged in a matrix of a plurality of rows and a plurality of columns, each memory transistor having four terminals;
- a plurality of first column lines, each first column line connecting a first terminal of all the memory transistors arranged in the same column;
- a plurality of second column lines, each second column line connecting a second terminal of all the memory transistors arranged in the same column;
- a plurality of third column lines, each third column line connecting a fourth terminal of all the memory transistors arranged in the same column;
- a plurality of row lines, each row line connecting a third terminal of all the memory transistors arranged in the same row;
- said memory transistors arranged in the same column having the same first, second and third column lines, with a third column line for the memory transistors arranged in a column being common with a first column line for the memory transistors arranged in an adjacent column;
- column decoding means for receiving a column address signal and for selecting one of a plurality of first and second column lines in response thereto;
- high voltage column decoding means coupled to said plurality of first column lines for selecting one of said first column lines;
- row decoding means for receiving a row address signal and for selecting one of a plurality of row lines in response thereto;
- high voltage row decoding means coupled to said plurality of row lines for selecting one of said row lines;
- and
- high voltage source, coupled to said high voltage column decoding means for supplying a high voltage source to a selected first column line, and coupled to said high voltage row decoding means for supplying a high voltage source to a select row line.
10 more elements
An electrically erasable and programmable read only memory array, said memory array comprising:
- a semiconductor substrate;
- a plurality of floating gate memory transistors arranged in a matrix of a plurality of rows and a plurality of columns, each memory transistor having four terminals;
- a plurality of first column lines, each first column line connecting a first terminal of all the memory transistors arranged in the same column;
- a plurality of second column lines, each second column line connecting a second terminal of all the memory transistors arranged in the same column;
- a plurality of third column lines, each third column line connecting a fourth terminal of all the memory transistors arranged in the same column;
- a plurality of row lines, each row line connecting a third terminal of all the memory transistors arranged in the same row;
- said memory transistors arranged in the same column having the same first, second and third column lines, with a third column line for the memory transistors arranged in a column being common with a third column line for the memory transistors arranged in a first adjacent column, and with a first column line for the memory transistors arranged in a column being common with a first column line for the memory transistors arranged in a second adjacent column;
- column decoding means for receiving a column address signal and for selecting one of a plurality of first and second column lines in response thereto;
- high voltage column decoding means for selecting one of said first column lines;
- row decoding means for receiving a row address signal and for selecting one of a plurality of row lines in response thereto;
- high voltage row decoding means for selecting one of said row lines;
- and
- high voltage source, coupled to said high voltage column decoding means for supplying a high voltage source to a selected first column line, and coupled to said high voltage row decoding means for supplying a high voltage source to a select row line.
10 more elements
An electrically erasable and programmable read only memory array, said memory array comprising:
- a semiconductor substrate;
- a plurality of first column lines;
- a plurality of first floating gate memory cells, each having a first terminal, and arranged in a plurality of columns;
- each first column line connecting said first terminal of all the first floating gate memory cells arranged in the same column;
- a plurality of second column lines, interspersed among said plurality of first column lines,
- a plurality of second floating gate memory cells, each having a first terminal, and arranged in a plurality of columns;
- each second column line connecting a first terminal of all the second floating gate memory cells arranged in the same column;
- said second floating gate memory cells arranged in the same column being programmed to the same state;
- means for connecting said second column lines to a voltage source,
- a plurality of first row lines, each first row line connecting a second terminal of all the floating gate memory cells arranged in the same row;
- said floating gate memory cells arranged in the same row having the same first row lines;
- column decoding means connected to said first column lines and for receiving a column address signal and for selecting one of a plurality of first column lines in response thereto;
- and
- row decoding means for receiving a row address signal and for selecting one of a plurality of first, row lines in response thereto.
11 more elements
Dependencies are inferred from the claim text.