Ferroelectric memory and method for controlling operation of the same

A method for controlling an operation of a ferroelectric memory which comprises, a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of unitary memory cell arrays each arranged along a corresponding one pair of data signal lines of said plurality of pairs of data signal lines, each of said unitary memory cell arrays including:

• a plurality of memory cells each including a ferroelectric capacitor having a capacitor dielectric composed of a ferroelectric material and sandwiched between a pair of opposing electrodes, a switching means connected to said ferroelectric capacitor and one of said corresponding pair of data signal lines, and controlled by a corresponding one of said selection signal lines, so that different polarized conditions of said ferroelectric capacitor correspond to different conditions of stored data, respectively, and when a first voltage, which is not zero, is applied between the opposing electrodes of said ferroelectric capacitor, since a current flowing between said ferroelectric capacitor and the corresponding data signal line is different dependently upon the polarized condition of said ferroelectric capacitor, the current is detected or a voltage appearing on the corresponding pair of data signal lines due to the current is detected for the purpose of reading out the stored data;
• a means connected to the corresponding one pair of data signal lines, for detecting said current or said voltage difference appearing between the corresponding pair of data signal lines,
• at least enough of said memory cells connected to each one data signal line to adjust a parasitic capacitance of each said data signal line, when data is read out from a memory cell, so as to minimize a variation of the voltage on said at least one of the corresponding pair of data signal lines caused by said parasitic capacitance,
• the method performing the reading of data from said memory cell to be read out, by setting the corresponding data signal line connected to said memory cell to be read out, to a second voltage, by setting a plate line connected to said memory cell to be read out, to a third voltage which is different from said second voltage and also different from a fourth voltage before the data reading operation, by setting said selection signal line connected to said memory cell to be read out, to a fifth voltage for selecting said memory cell to be read out, so that a voltage difference is caused to occur between the opposing electrodes of said ferroelectric capacitor, whereby a signal corresponding to the data stored in said memory cell to be read out is outputted to the corresponding data signal line.

A method for controlling an operation of a ferroelectric memory which comprises, a plurality of pairs of data signal lines for outputting and receiving data, a plurality of selection signal lines selected in accordance with an address signal, and a plurality of unitary memory cell arrays each arranged along a corresponding one pair of data signal lines of said plurality of pairs of data signal lines, each of said unitary memory cell arrays including:

• a plurality of memory cells each including a ferroelectric capacitor having a capacitor dielectric composed of a ferroelectric material and sandwiched between a pair of opposing electrodes, a switching means connected to said ferroelectric capacitor and one of said corresponding pair of data signal lines, and controlled by a corresponding one of said selection signal lines, so that different polarized conditions of said ferroelectric capacitor correspond to different conditions of stored data, respectively, and when a first voltage, which is not zero, is applied between the opposing electrodes of said ferroelectric capacitor, since a current flowing between said ferroelectric capacitor and the corresponding data signal line is different dependently upon the polarized condition of said ferroelectric capacitor, the current is detected or a voltage appearing on the corresponding pair of data signal lines due to the current is detected for the purpose of reading out the stored data;
• a means connected to the corresponding one pair of data signal lines, for detecting said current or said voltage difference appearing between the corresponding pair of data signal lines,
• at least enough of said memory cells connected to each one data signal line to adjust a parasitic capacitance of each said data signal line, when data is read out from a memory cell, so as to minimize a variation of the voltage on said at least one of the corresponding pair of data signal lines caused by said parasitic capacitance,
• the method performing the reading of data from said memory cell to be read out, by setting the corresponding data signal line connected to said memory cell to be read out, to a second voltage, by setting a plate line connected to said memory cell to be read out, to a third voltage which is a fixed voltage different from said second voltage, by setting said selection signal line connected to said memory cell to be read out, to a fourth voltage for selecting said memory cell to be read out, so that a voltage difference is caused to occur between the opposing electrodes of said ferroelectric capacitor, whereby a signal corresponding to the data stored in said memory cell to be read out is outputted to the corresponding data signal line.