US 5,668,750 A · Bipolar multiplier with wide input voltage range using multitail cell · patentgrep

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Abstract

A bipolar four-quadrant analog multiplier that is formed on a semiconductor integrated circuit device and is capable of low-voltage operation at a voltage as low as 1 V while the input voltage range providing a good linearity is enlarged. This multiplier contains a multitail cell made of a first transistor pair of first and second bipolar transistors, a second transistor pair of third and fourth bipolar transistors, and at least one bipolar transistor. The first and second transistors have output ends coupled together to form one of differential output ends of the multiplier. The third and fourth transistors have output ends coupled together to form the other of the differential output ends. The first to fifth transistors are driven by a common tail current. The first, second, third, fourth and fifth transistors are applied with (aV.sub.x +bV.sub.y), [(a-1)V.sub.x +(b-1)V.sub.y ], [(a-1)V.sub.x +bV.sub.y ], [aV.sub.x +(b-1)V.sub.y ], and [{a-(1/2}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c ], respectively, where V.sub.x and V.sub.y are initial input signals to be multiplied, a and b are constants, and V.sub.c is a positive dc voltage.

Claims29

Dependent claims

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of {a-(1/2)}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c, where V.sub.c is a positive dc voltage;
and
(d) said first transistor pair, said second transistor pair, and said fifth bipolar transistor being driven by a common tail current, thereby forming a multitail cell:
(e) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

11 more elements

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of {a-(1/2)}V.sub.x +{b-(1/2)}V.sub.y +4V.sub.T .multidot.ln2, where V.sub.c is a positive dc voltage;
(d) a sixth bipolar transistor having an input end and an output end;
said input end of said sixth transistor being applied with a sixth input signal of aV.sub.x +{b-(1/2)}V.sub.y +2V.sub.T .multidot.ln2;
(e) a seventh bipolar transistor having an input end and an output end;
said input end of said seventh transistor being applied with a seventh input signal of (a-1)V.sub.x +{b-(1/2)}V.sub.y +2V.sub.T .multidot.ln2;
(f) an eighth bipolar transistor having an input end and an output end;
said input end of said eighth transistor being applied with an eighth input signal of {a-(1/2)}V.sub.x +bV.sub.y +2V.sub.T .multidot.ln2;
and
(g) a ninth bipolar transistor having an input end and an output end;
said input end of said ninth transistor being applied with a ninth input signal of {a-(1/2)}V.sub.x +(b-1)V.sub.y +2V.sub.T .multidot.ln2;
(h) said output ends of said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, and said ninth bipolar transistor being coupled together:
(i) said first transistor pair, said second transistor pair, said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, and said ninth bipolar transistor being driven by a common tail current, thereby forming a multitail cell:
(j) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

20 more elements

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of aV.sub.x +{b-(1/2)(1-5.sup.-1/2)}V.sub.y +V.sub.c, where V.sub.c is a positive dc voltage;
(d) a sixth bipolar transistor having an input end and an output end;
said input end of said sixth transistor being applied with a sixth input signal of (a-1)V.sub.x +{b-(1/2)(1-5.sup.-1/2)}V.sub.y +V.sub.c ;
(e) a seventh bipolar transistor having an input end and an output end;
said input end of said seventh transistor being applied with a seventh input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +bV.sub.y +V.sub.c ;
(f) an eighth bipolar transistor having an input end and an output end;
said input end of said eighth transistor being applied with an eighth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +(b-1)V.sub.y +V.sub.c ;
(g) a ninth bipolar transistor having an input end and an output end;
said input end of said ninth transistor being applied with a ninth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +{b-(1/2)(1-5.sup.-1/2)}V.sub.y +2V.sub.c ;
(h) a tenth bipolar transistor having an input end and an output end;
said input end of said tenth transistor being applied with a tenth input signal of {a-(1/2)(1+5.sup.-1/2)}V.sub.x +{b-(1/2)(1+5.sup.-1/2)) V.sub.y +2V.sub.c ;
(i) an eleventh bipolar transistor having an input end and an output end;
said input end of said eleventh transistor being applied with an eleventh input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +{b-(1/2)(1+5.sup.-1/2)}V.sub.y +2V.sub.c ;
(j) a twelfth bipolar transistor having an input end and an output end;
said input end of said twelfth transistor being applied with a twelfth input signal of {a-(1/2)(1+5.sup.-2/1)}V.sub.x +{b-(1/2)(1-5.sup.-1/2)}V.sub.y +2V.sub.c ;
(k) a thirteenth bipolar transistor having an input end and an output end;
said input end of said thirteenth transistor being applied with a thirteenth input signal of aV.sub.x +{b-(1/2)(1+5.sup.-1/2)}V.sub.y +V.sub.c ;
(l) a fourteenth bipolar transistor having an input end and an output end;
said input end of said fourteenth transistor being applied with a fourteenth input signal of (a-1)V.sub.x +(b-(1/2)(1-5.sup.-1/2)) V.sub.y +V.sub.c ;
(m) a fifteenth bipolar transistor having an input end and an output end;
said input end of said fifteenth transistor being applied with a fifteenth input signal of {a-(1/2)(1+5.sup.-1/2)}V.sub.x +(b-1)V.sub.y +V.sub.c ;
and
(n) a sixteenth bipolar transistor having an input end and an output end;
said input end of said sixteenth transistor being applied with a sixteenth input signal of {a-(1/2)(1+5.sup.-1/2)}V.sub.x +bV.sub.y +V.sub.c ;
(o) said output ends of said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, said ninth bipolar transistor, said tenth bipolar transistor, said eleventh bipolar transistor, said twelfth bipolar transistor, said thirteenth bipolar transistor, said fourteenth bipolar transistor, said fifteenth bipolar transistor, and said sixteenth bipolar transistor being coupled together:
(p) said first transistor pair, said second transistor pair, said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, said ninth bipolar transistor, said tenth bipolar transistor, said eleventh bipolar transistor, said twelfth bipolar transistor, said thirteenth bipolar transistor, said fourteenth bipolar transistor, said fifteenth bipolar transistor, and said sixteenth bipolar transistor being driven by a common tail current, thereby forming a multitail cell:
(q) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

34 more elements

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of {(a-(1/2)}V.sub.x +bV.sub.y +2V.sub.c, where V.sub.c is a positive dc voltage;
(d) a sixth bipolar transistor having an input end and an output end;
said input end of said sixth bipolar transistor being applied with a sixth input signal of {a-(1/2)}V.sub.x +b-1)V.sub.y +2V.sub.c ;
said output end of said sixth bipolar transistor is connected to said output end of said fifth bipolar transistor;
(e) said first transistor pair, said second transistor pair, said fifth bipolar transistor, and said sixth bipolar transistor being driven by a common tail current, thereby forming a multitail cell:
(f) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

13 more elements

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of aV.sub.x +{b-(1/2)(1-5.sup.-1/2)V.sub.y }+V.sub.c where V.sub.c is a positive dc voltage;
(d) a sixth bipolar transistor having an input end and an output end;
said input end of said sixth bipolar transistor being applied with a sixth input signal of (a-1)V.sub.x +{b-(1/2)(1-5.sup.-1/2)V.sub.y }+V.sub.c ;
(e) a seventh bipolar transistor having an input end and an output end;
said input end of said seventh bipolar transistor being applied with a seventh input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +(b-1)V.sub.y +V.sub.c ;
(f) an eighth bipolar transistor having an input end and an output end;
said input end of said eighth bipolar transistor being applied with an eighth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +bV.sub.y +V.sub.c ;
(g) said output ends of said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, and said eighth bipolar transistor being coupled together;
(h) said first transistor pair, said second transistor pair, said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, and said eighth bipolar transistor being driven by a common tail current, thereby forming a multitail cell;
(i) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

17 more elements

A bipolar multiplier for multiplying a first initial input signal V.sub.x and a second initial input signal V.sub.y, said multiplier comprising:

(a) a first transistor pair of a first bipolar transistor having an input end and an output end and a second bipolar transistor having an input end and an output end;
said output ends of said first bipolar transistor and said second bipolar transistor being coupled together, thereby forming one of differential output ends of said multiplier;
said input end of said first bipolar transistor being applied with a first input signal of (aV.sub.x +bV.sub.y), where a and b are constants;
said input end of said second bipolar transistor being applied with a second input signal of (a-1)V.sub.x +(b-1)V.sub.y ;
(b) a second transistor pair of a third bipolar transistor having an input end and an output end and a fourth bipolar transistor having an input end and an output end;
said output ends of said third bipolar transistor and said fourth bipolar transistor being coupled together, thereby forming the other of said differential output ends of said multiplier;
said input end of said third bipolar transistor being applied with a third input signal of (a-1)V.sub.x +bV.sub.y ;
said input end of said fourth bipolar transistor being applied with a fourth input signal of aV.sub.x +(b-1)V.sub.y ;
and
(c) a fifth bipolar transistor having an input end and an output end;
said input end of said fifth bipolar transistor being applied with a fifth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +bV.sub.y +V.sub.c2, where V.sub.c2 is a positive dc voltage;
(d) a sixth bipolar transistor having an input end and an output end;
said input end of said sixth transistor being applied with a sixth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +{b-1}V.sub.y +V.sub.c2 ;
(e) a seventh bipolar transistor having an input end and an output end;
said input end of said seventh transistor being applied with a seventh input signal of aV.sub.x +{b-(1/2)}V.sub.y +V.sub.c1, where V.sub.c1 is a positive dc voltage;
(f) an eighth bipolar transistor having an input end and an output end;
said input end of said eighth transistor being applied with an eighth input signal of (a-1)V.sub.x +{b-(1/2)}V.sub.y +V.sub.c1 ;
(g) a ninth bipolar transistor having an input end and an output end;
said input end of said ninth transistor being applied with a ninth input signal of {a-(1/2)(1-5.sup.-1/2)}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c3, where V.sub.c3 is a positive dc voltage;
(h) a tenth bipolar transistor having an input end and an output end;
said input end of said tenth transistor being applied with a tenth input signal of {a-(1/2)(1+5.sup.-1/2)}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c3 ;
(i) an eleventh bipolar transistor having an input end and an output end;
said input end of said eleventh transistor being applied with an eleventh input signal of {a-(1/2)(1+5.sup.-1/2)}V.sub.x +{b-(1/2)}V.sub.y +V.sub.c3 ;
(j) a twelfth bipolar transistor having an input end and an output end;
said input end of said twelfth transistor being applied with a twelfth input signal of {a-(1/2)(1+5.sup.-2/1)}V.sub.x +bV.sub.y +V.sub.c2 ;
(k) said output ends of said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, said ninth bipolar transistor, said tenth bipolar transistor, said eleventh bipolar transistor, and said twelfth bipolar transistor being coupled together;
(l) said first transistor pair, said second transistor pair, said fifth bipolar transistor, said sixth bipolar transistor, said seventh bipolar transistor, said eighth bipolar transistor, said ninth bipolar transistor, said tenth bipolar transistor, said eleventh bipolar transistor, and said twelfth bipolar transistor being driven by a common tail current, thereby forming a multitail cell;
(m) wherein the multiplication result V.sub.x .multidot.V.sub.y of said first initial input signal V.sub.x and said second initial input signal V.sub.y is differentially output from said differential output ends.

25 more elements

Dependencies are inferred from the claim text.