Circuit for performing arithmetic operations in a demodulator

A multi-task arithmetic unit for performing various arithmetic operation, the multi-task arithmetic unit comprising:

• an in-phase register;
• a quadrature register;
• an angular register;
• a first multiplexer operably coupled to the in-phase register, the quadrature register, and the angular register;
• a second multiplexer operably coupled to the in-phase register and the quadrature register;
• first shift register operably coupled to the first multiplexer, wherein the first shift register performs at least part of multiplication operations;
• second shift register operably coupled to the second multiplexer, wherein the second shift register performs at least part of multiplication operations;
• first adder operably coupled to the first shift register and the second shift register;
• accumulator register operably coupled to an output of the first adder, the in-phase register, the quadrature register, the angular register and the first multiplexer;
• and
• controller that provides control signals to the in-phase register, the quadrature register, the angular register, the first multiplexer, the second multiplexer, the first shift register, the second shift register, the first adder, and the accumulator register, wherein, based on the control signals, various arithmetic operations are performed.

A parallel processor for performing various arithmetic operation, the parallel processor comprising:

• a plurality of multi-task arithmetic units, each of the plurality of multi-task arithmetic units includes:
• an in-phase register;
• a quadrature register;
• an angular register;
• a first multiplexer operably coupled to the in-phase register, the quadrature register, and the angular register;
• a second multiplexer operably coupled to the in-phase register and the quadrature register;
• first shift register operably coupled to the first multiplexer, wherein the first shift register performs at least part of multiplication operations;
• second shift register operably coupled to the second multiplexer, wherein the second shift register performs at least part of multiplication operations;
• first adder operably coupled to the first shift register and the second shift register;
• accumulator register operably coupled to an output of the adder, the in-phase register, the quadrature register, the angular register and the first multiplexer;
• data bus operably coupled to each multi-task arithmetic unit;
• memory operably coupled to each multi-task arithmetic unit;
• dynamic memory operably coupled to each multi-task arithmetic unit;
• and
• controller that provides control signals to each of the plurality of multi-task arithmetic units, wherein, based on the control signals, various arithmetic operations are performed by the parallel processor.