Apparatus for two-dimensional discrete cosine transform
AssigneeUnited Microelectronics Corp.
InventorPo-Chuan Huang
Life of this patent
Estimating the term…
Abstract
An apparatus for real time 2-D DCT comprises a rate buffer, a pair of multiplexers, a plurality of registers, a plurality of summing elements, a plurality of parameter extractors, a plurality of accumulators, a pair of truncators, a transpose buffer and an inverse rate buffer. In the present invention, data input rate of the rate buffer and output rate of the inverse rate buffer are a first rate, while the transform process, which is carried out between the rate buffer and the inverse rate buffer, is at a second rate. Moreover, a distributed arithmetic structure is utilized in the invention to decrease the circuit complexity and increase the operating efficiency. Therefore, real time 2-D DCT can be achieved by the apparatus of the present invention.
Claims11
An apparatus for real time two-dimensional (2-D) discrete cosine transform (DCT) comprising:
- a rate buffer for inputting an N.times.N data at a first rate and outputting said data at a second rate;
- a first multiplexer for providing either a first data path or a second data path for data transmission said first data path being provided for said data from said rate buffer during a first 1-D DCT process, while during a second 1-D DCT process, said second data path is provided for a transposed data;
- N first registers connected in series, one of said first registers being connected to said first multiplexer for sequentially writing the data provided by said first multiplexer to a next said first register;
- a second multiplexer for providing either a third data path for data from said first register which is connected to said first multiplexer or a fourth data path for a feedback data;
- NB 2 summing elements connected to said first registers for subtracting and adding the data provided by said first registers and said second multiplexer;
- N second registers for storing data from said summing elements;
- N parameter extractors for generating parameters by the data stored in said second registers;
- N accumulators for accumulating as transformed data the parameters of said parameter extractors;
- a transpose buffer for transposing said transformed data from said accumulators;
- wherein said transposed data is generated by said transpose buffer and is stored therein during said first 1-D DCT process;
- and
- an inverse rate buffer for acquiring data from said accumulators, during said second 1-D DCT process, at said second rate, and outputting an N.times.N data at said first rate.
Dependencies are inferred from the claim text.