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US 5,668,732 AGranted
Method for estimating power consumption of a cyclic sequential electronic circuit
AssigneeSynopsys, Inc.
InventorsAdel Khouja, Shankar Krishnamoorthy, Frederic G. Mailhot, Stephen F. Meier
Life of this patent
Estimating the term…
Abstract
This is a method of quickly computing the power dissipated by a digital circuit using information available at the gate library level. It estimates the short-circuit power by modeling the energy dissipated by the cell per input transition as a function of the transition time or edge rate, and multiplying that value by the number of transitions per second for that input.
Claims28
A method for estimating average power consumption of an electronic circuit that includes sequential elements represented as a netlist stored in an electronic memory comprising the steps of:
- producing in the electronic memory a graph representing the electronic circuit in which sequential elements are represented as nodes and combinational logic elements connected between sequential elements are represented as directed arcs;
- removing from the graph a first node that forms part of a cyclic path within the graph and that represents a first sequential element of the electronic circuit;
- producing in the graph a first source node that represents the first sequential element of the electronic circuit;
- producing in the graph a first load node that represents the first sequential element of the electronic circuit;
- producing in the graph a respective corresponding first source arc that represents a respective arc output from the removed first node, each respective first source arc having the first source node as its origin and having a destination that is the same as its corresponding arc output of the removed first node;
- producing in the graph a respective corresponding first load arc that represents a respective arc input to the removed first node, each respective first load arc having the first load node as its destination and having a source that is the same as its corresponding arc input to the removed first node;
- grouping the nodes and the arcs of the graph into respective graph levels, each corresponding to a respective group of sequential logic of the electronic circuit and to a respective group of combinational logic of the electronic circuit that feeds such respective group of sequential logic wherein groups of deeper levels within the graph feed signals to groups of less deep levels;
- and
- computing respective switching activity values for nets of the netlist in an order prescribed by the graph by computing switching activity values for nets of a respective group of nets representing a respective group of combinatorial logic corresponding to a given graph level, using as respective primary inputs to the respective group of nets, switching activity values computed for another respective group of nets representing a respective group of deeper logic level combinatorial logic corresponding to a respective deeper graph level.
6 more elements
A method for estimating average power consumption of an electronic circuit that includes sequential elements represented as a netlist stored in an electronic memory comprising the steps of:
- producing in the electronic memory a graph representing the electronic circuit in which sequential elements are represented as nodes and combinational logic elements connections between sequential elements are represented as directed arcs;
- removing from the graph a first node that forms part of a cyclic path within the graph and that represents a first sequential element of the electronic circuit;
- producing in the graph a first source node that represents the first sequential element of the electronic circuit;
- producing in the graph a first load node that represents the first sequential element of the electronic circuit;
- producing in the graph a respective corresponding first source are that represents a respective arc output from the removed first node, each respective first source are having the first source node as its origin and having a destination that is the same as its corresponding arc output of the removed first node;
- producing in the graph a respective corresponding first load arc that represents a respective arc input to the removed first node, each respective first load arc having the first load node as its destination and having a source that is the same as its corresponding arc input to the removed first node;
- grouping the nodes and the arcs of the graph into respective graph levels, each corresponding to a respective group of sequential logic of the electronic circuit and to a respective group of combinational logic of the electronic circuit that feeds such respective group of sequential logic;
- and
- computing respective switching activity values for nets of the netlist in an order prescribed by the graph levels such that computation of respective switching activity values for given logic corresponding to a given graph level uses a switching activity of a prior node computed from prior logic corresponding to a prior graph level as a basis for a primary input to such given logic.
6 more elements
In a computer system including a computer readable memory, a method for propagating signal probability across sequential cells for power consumption computations, said method comprising the steps of:
- a) generating an element graph in said computer readable memory, said element graph containing (1) a node for each sequential cell and each primary input of a circuit represented by a netlist and (2) a directed arc for each combinational logic element, wherein directed arcs are coupled between nodes;
- b) identifying self-loop nodes within said element graph;
- c) breaking loop nodes in said element graph wherein a predetermined loop node is selected and replaced with corresponding source and sink nodes, said step c) generating an acyclic element graph;
- d) levelizing said acyclic element graph wherein nodes of said acyclic element graph are indicated with respective level values;
- e) assigning static probabilities and toggle rates to inputs of each combinational logic circuit of said netlist that corresponds to a directed arc in said acyclic element graph that originates from any level 0 (zero) node or from any primary input;
- f) computing toggle rates and static probabilities of internal nets of said combinational logic that terminate at a node having a level value equal to a current level counter value;
- and
- g) computing toggle rates and static probabilities of outputs of each sequential cell of said netlist at a node having a level value equal to said current level counter value.
5 more elements
A computer system including a computer readable memory containing instructions that when executed causing said computer system to implement a method for propagating signal probability across sequential cells for power consumption computations, said method comprising the steps of:
- a) generating an element graph in said computer readable memory, said element graph containing (1) a node for each sequential cell and each primary input of a circuit represented by a netlist and (2) a directed arc for each combinational logic element, wherein directed arcs are coupled between nodes;
- b) identifying self-loop nodes within said element graph;
- c) breaking loop nodes in said element graph wherein a predetermined loop node is selected and replaced with corresponding source and sink nodes, said step c) generating an acyclic element graph;
- d) levelizing said acyclic element graph wherein nodes of said acyclic element graph are indicated with respective level values;
- e) assigning static probabilities and toggle rates to inputs of each combinational logic circuit of said netlist that corresponds to a directed arc in said acyclic element graph that originates from any level 0 node or from any primary input;
- f) computing toggle rates and static probabilities of internal nets of said combinational logic that terminate at a node having a level value equal to a current level counter value;
- and
- g) computing toggle rates and static probabilities of outputs of each sequential cell of said netlist at a node having a level value equal to said current level counter value.
5 more elements
Dependencies are inferred from the claim text.