Video circuit for generating special fast dynamic displays

A method for generating fast temporal modulation of an arbitrary number of screen areas on a video display in accordance with a plurality of mutually orthogonal binary sequences belonging to a Hadamard set, each of said binary sequences of said Hadamard set being defined by the series of parities of the bitwise logic AND between a complete non-repetitive sequence of binary words of a predetermined length and a fixed binary word of said predetermined length, said method comprising:

• providing a video memory which is able to store k bits of video data for every pixel on said video display, where k is an integer,
• initializing each of said screen areas by loading the corresponding locations in said video memory with said fixed binary word of said predetermined length, fixed binary word of said predetermined length defining one of said binary sequences belonging to said Hadamard set,
• providing at least one k-stage binary mask register each having k outputs, one for each stage of said mask register, where each output is arranged to supply a binary signal,
• sequentially loading at least one of said mask registers between frames of said video display with said complete nonrepetitive sequence of binary words of said predetermined length, said mask registers thereby having binary ONEs and ZEROs,
• providing, for each one of said mask registers, a circuit generating the parity of a subset of said k bits of video data, such that said binary ONEs in said mask register specify said subset, and
• providing a pixel means for controlling each pixel on said video display in accordance with said pities.

A circuit for rapidly generating sequences of 2.sup.n different video frames on a display having a predetermined number of pixels, comprising:

• a video memory which is able to store k bits of video data for every pixel on said display, where k is an integer, and
• a circuit for generating the parity of a specified subset of said k bits of video data, said circuit comprising:
• a k-bit binary register mask register having k outputs, one for each bit of said register, where each output is arranged to supply a binary signal,
• a circuit providing, for each pixel on said display, a bit-wise logic AND function between said binary signal and said video data,
• a parity generator for deriving a parity signal from the result of said bit-wise logic AND function, and
• a switching circuit controlled by said parity signal, said switching circuit being arranged to select, for said pixels of said display, one of two predetermined voltage levels, said voltage levels being selected to determine the brightness of said pixels of said display.