Comparator circuit using two bit to four bit encoder

A comparator circuit for comparing a first address comprising at least two bits to a second address comprising an equal number of corresponding bits as said first address to determine if said first address equals said second address, said comparator circuit comprising:

• means for encoding each two bits of said first address into a first four bit representation wherein each bit has an on state and an off state and only one of the four bits is in said on state and said second address into a second four bit representation wherein each bit corresponds to a bit from said first four bit representation and has an on state and an off state and wherein only one of the four bits is in said on state;
• four AND gates, each having a pair of inputs and an output per each of said first and second four bit representations for ANDing each single bit of said first four bit representation with a bit of said second four bit representation corresponding to said single bit of said first four bit representation;
• and
• one OR gate per each of said first and second four bit representations for ORing each said output of said AND gates.

A comparator circuit for comparing a first address comprising at least two bits to a second address comprising an equal number of corresponding bits as said first address to determine if said first address is not equal to said second address, said comparator circuit comprising:

• means for encoding each two bits of said first address into a first four bit representation wherein each bit has an on state and an off state and only one of the four bits is in said on state and said second address into a second four bit representation wherein each bit corresponds to a bit from said first four bit representation and has an on state and an off state and wherein only one of the four bits is in said on state;
• four OR gates, each having three inputs and an output per each of said OR gates for ORing three of the four bits of said first four bit representation;
• and
• one AND gate having a first input, a second input and an output per each of said OR gates for ANDing said output of each said OR gate with a selected bit from said second four bit representation wherein said selected bit corresponds to the bit of said first four bit representation which was not ORed by said OR gate.

A method for comparing a first and second address, an address being represented by a number of binary logic bits, the method comprising:

• grouping the bits of the first and second address into certain corresponding sets;
• encoding a set into a corresponding encoded set, wherein only one bit of the encoded set has a predefined logic state;
• and
• comparing bits of an encoded set of the first address with corresponding bits of the corresponding encoded set of the second address.