Controlling FPLL polarity using pilot signal and polarity inverter
AssigneeZenith Electronics Corporation
InventorGary J. Sgrignoli
Life of this patent
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Abstract
A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.
Claims14
A method of demodulating a digital signal including an in-phase pilot, in the form of a DC offset voltage, comprising:
- applying the digital signal to a biphase stable FPLL for demodulation;
- recovering the DC pilot;
- and
- supplying an output demodulated signal of predetermined polarity as determined by the polarity of the recovered pilot.
A circuit for receiving a digital signal including an in-phase pilot, in the form of a DC offset voltage, demodulating the digital signal, recovering the pilot and providing an output signal to a signal processor, comprising:
- a biphase stable FPLL for receiving said digital signal and for recovering said pilot and generating a demodulated signal;
- a biphase stable FPLL for receiving said digital signal and for recovering said pilot and generating a demodulated signal;
- polarity determination means for determining from said recovered pilot, the polarity of said demodulated signal;
- and
- inverting means, responsive to said polarity determination means, for assuring that said output signal supplied to said signal processor has a predetermined polarity.
Dependencies are inferred from the claim text.