Back to results
US 5,668,495 AGranted
BiCMOS reprogrammable logic
AssigneeDynaChip Corporation
InventorsMadhukar B. Vora, Burnell G. West
Life of this patent
Estimating the term…
Abstract
A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.
Claims9
A crossbar switch, comprising:
- a plurality of high speed signal inputs for receiving high speed data signals;
- a first multiplexer having a plurality of data inputs equal in number to the number of said plurality of high speed signal inputs and each coupled to one of said plurality of high speed signal inputs, said first multiplexer having a shared data output, said first multiplexer comprised of a plurality of switching devices each of which is coupled to one of said plurality of high speed signal inputs via a corresponding one of said data inputs of said first multiplexer, and each of said plurality of switching devices having an enabling circuit coupled thereto for receiving a steering signal assigned to that switching device so as to individually enable said switching device, said enabling circuitry controlled by a steering signal assigned to that switching device so as to be able to drive said shared data output of said first multiplexer in accordance with data received at the corresponding high speed signal input to which said switching device is coupled;
- one or more other multiplexers, each having a corresponding plurality of data inputs equal in number to the number of said high speed signal inputs, each of said plurality of data inputs of said one or more other multiplexers coupled to one of said plurality of high speed signal inputs, and each of said one or more other multiplexers having a shared data output, each of said one or more other multiplexers comprised of a plurality of switching devices each of which has a data input which is coupled to a data input of the one of said one or more other multiplexers of which said switching device is a part, each of said switching devices of said one or more other multiplexers including an enabling circuit coupled thereto, said enabling circuit controlled by a steering signal assigned to that switching device so as to individually enable the switching device to which said enabling circuit is coupled in response to said steering signal assigned to said switching device, so as to control said switching device to drive the shared data output of the multiplexer of which the switching device so enabled is a part in response to the data received at the high speed signal input to which said switching device is coupled, such that by proper manipulation of said steering signals for said first multiplexer and said one or more other multiplexers, each of the shared outputs can be driven with signals received at any one of said high speed signal inputs so long as no more than one high speed signal input is used to drive any shared data output at any particular time;
- and wherein each of said switching devices coupled to one of said plurality of data inputs in said first multiplexer and each of said switching devices coupled to one of said plurality of data inputs of said one or more other multiplexers comprises a high speed, differential pair of bipolar transistors controlling data flow in the data path between said high speed signal inputs and said shared data outputs and wherein each said differential pair of bipolar transistors has a common emitter node and is integrated on an integrated circuit with the corresponding enabling circuit to which said switching device is coupled, and wherein each said enabling circuit is comprised of integrated CMOS transistors which are coupled to said common emitter node of the differential pair of bipolar transistors to which said enabling circuit is coupled, said CMOS transistors for selectively coupling either a first voltage to said common emitter node when the steering signal assigned to said switching device is in a first logical state so as to enable said switching device or coupling a second voltage to said common emitter node when said steering signal is in a second logical state so as to disable said switching device, thereby keeping said CMOS transistors of said enabling circuit of each switching device out of the high speed signal data path between any of said high speed signal inputs and any of said shared data outputs.
1 more element
A semiconductor integrated circuit, comprising:
- a high reference conductor for coupling to a first voltage supply;
- a low reference conductor for coupling to a second voltage supply, said second voltage being lower than said first voltage;
- an enable input for receiving an enable signal;
- a first bipolar transistor having a base, a collector and an emitter and a base-emitter junction, said collector for coupling to said high reference conductor;
- a current source having a first terminal coupled to said emitter of said first bipolar transistor and having a second terminal;
- a first MOS transistor means having source and drain terminals coupled to said low reference conductor and said second terminal of said current source, respectively, and having a gate terminal coupled to said enable input, for cutting off current flow between said second terminal of said current source and said low reference conductor thereby disabling said first bipolar transistor when said enable signal is in a first logical state and for allowing current to flow between said current source and said low reference conductor thereby enabling said first bipolar transistor when said enable signal is in a second logical state;
- and
- a second MOS transistor means having a gate terminal coupled to said enable input, said second MOS transistor means having source and drain terminals coupled to said first bipolar transistor in such a way so as to be able to affect the voltage drop across said base-emitter junction, said second MOS transistor means for immediately forcing an alteration of the voltage drop across said base-emitter junction of said first bipolar transistor so as to cut off conduction between said collector and said emitter thereof thereby disabling said first bipolar transistor when said enable signal is placed in said first logical state, and, when said enable signal is in said second logical state, for ceasing to force an alteration of the voltage drop across said base-emitter junction of said first bipolar transistor so that said bipolar transistor is no longer disabled.
5 more elements
A method of disabling a bipolar transistor coupled by a current source to a first reference voltage source and having a collector coupled to a second reference voltage source which outputs a voltage higher than the voltage output by said first reference voltage source, comprising:
- using a first MOS transistor having source and drain terminals connected between said current source and said first reference voltage to cut off current flow between said current source and said first reference voltage source by appropriate setting of the logic state of an enable signal applied to a gate terminal of said first MOS transistor;
- and
- using a second MOS transistor to reverse bias a base-emitter junction of said bipolar transistor, said second MOS transistor having source and drain terminals coupled between said second reference voltage source and an emitter terminal of said bipolar transistor and having a gate coupled to receive said enable signal, by appropriately setting said logic state of said enable signal such that when said first MOS transistor is cutting off current flow between said current source and said low reference voltage source, said second MOS transistor is simultaneously coupling said second reference voltage to said emitter of said bipolar transistor thereby reverse biasing the base-emitter junction thereof.
Dependencies are inferred from the claim text.