Integrated circuit clocking technique and circuit therefor
AssigneeInternational Business Machines Corporation
InventorsMark Eric Pedersen, Peter Wohl
Life of this patent
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Abstract
A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan and functional clock signals adapted to the sequential circuits, which may have a variety of required timing diagrams.
Claims10
A circuit for selectively generating and distributing from a single system clock, a plurality of local clocks for scan testing an integrated circuit having a plurality of types of sequential circuits through which a scan path is connected, comprising:
- a first local clock generator located in close proximity to a first sequential circuit of a first type, for receiving and selectively gating the system clock responsive to a first control signal to provide to the first sequential circuit first scanning and functional clock signals;
- and
- a second local clock generator located in close proximity to a second sequential circuit of a second type, for receiving and selectively gating the system clock responsive to a second control signal to provide to the second sequential circuit second functional and scanning clocks.
Dependencies are inferred from the claim text.