Variable delay circuit

A variable delay circuit including:

• a gate chain comprising first to n-th delay gates (n is an integer larger than 2) connected in series via delay gate wirings, each of the delay gate wirings having the same wiring length, said first delay gate receiving an input signal for delay;
• and
• an n:1 separating selector having n inputs connected to respective outputs of said first to n-th delay gates, one of the inputs being selected in accordance with a select signal, said n:1 separating selector comprising:
• first to n-th separator gates respectively receiving outputs of said first to n-th delay gates;
• a selection gate to which outputs of said first to n-th separator gates are connected and outputting one of the outputs of said first to n-th separator gates;
• and
• first to n-th separator gate wirings respectively connecting outputs of said first to n-th separator gates to said selection gate, each of the first to n-th separator gate wirings having a length, the lengths of the separator gate wirings becoming successively shorter from said first separator gate to said n-th separator gate.

A variable delay circuit including:

• a gate chain comprising first to n-th delay gates (n is an integer larger than 2) connected in series via delay gate wirings, each of the delay gate wiring having the same wiring length, said first delay gate receiving an input signal for delay;
• first to n-th separator circuits to which outputs of said first to n-th delay gates of said gate chain are connected and including first to m-th separating system, respectively;
• and
• an (m.times.n):1 selector to which outputs of said first to n-th separator circuits are connected at (m.times.n) inputs for selecting one of the inputs in accordance with a select signal, each of said first to m-th separating systems including separator gates having respective inputs connected in common, and respective separator gate wirings having one end connected to an output of a corresponding separator gate and another end connected to one of the inputs of said (m.times.n):1 selector, the separator gate wirings becoming successively shorter from said first separating system of said first separator circuit to said m-th separating system of said n-th separator circuit for removing variations in the gate delay times of said first to n-th delay gates.

A variable delay circuit including:

• a gate chain comprising first to n-th delay gates (n is an integer larger than 2) connected in series via delay gate wirings, each of the delay gate wirings having the same wiring length, said first delay gate receiving an input signal for delay;
• and
• first to n-th separator circuits connected to respective outputs of said first to n-th delay gates of said gate chain and having first to m-th separating systems, respectively;
• and
• first to m-th n:1 selectors having n inputs respectively connected to corresponding outputs of each of said separator circuits at respective inputs for selecting one of the inputs in accordance with respective select signals, respectively, each of said first to m-th separating systems including a separator gate, said separator gates having respective inputs connected in common, and a separator gate wiring having one end respectively connected to an output of one of said separator gates and another end respectively connected to an input of one of said first to m-th n:1 selectors, the separator gate wirings of said first to n-th separator circuits becoming successively shorter from said first separator circuit to said n-th separator circuit, the separator gate wiring lengths among respective separating systems being different from each other.