US 5,668,490 AGranted

Flip-flop with full scan capability

AssigneeSun Microsystems, Inc.

InventorsSundari S. Mitra, David Greenhill, Philip A. Ferolito

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Abstract

A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal. During a first part of a scan clock cycle, the second switch closes, providing the scan-in signal to the master stage. The data stored in the master stage is provided to the fourth switch, connected between the master stage and the scan-out logic gate. During a second part of the scan clock cycle, the fourth switch closes, providing the data stored in the master stage to the scan-out logic gate, which outputs a scan-out signal.

Claims34

Dependent claims

A circuit comprising:

a first switch having a control lead, an input lead and an output lead, wherein said control lead of said first switch is adapted to receive a first clock signal, and said input lead of said first switch is adapted to receive a first data signal;
a master stage having an input lead and an output lead, said input lead of said first stage coupled to said output lead of said first switch, wherein said master stage is capable of storing a logic value dependent on a logic state of a master-in signal received at said input lead of said master stage and of outputting a master-out signal at said output lead of said master stage having a logic state dependent on said logic value stored in said master stage;
a second switch having a control lead, an input lead and an output lead, wherein said control lead of said second switch is adapted to receive a second clock signal, said input lead of said second switch is adapted to receive a second data signal, and said output lead of said second switch is coupled to said input lead of said master stage;
a third switch having a control lead, an input lead and an output lead, wherein said control lead of said third switch is adapted to receive said first clock signal, and said input lead of said third switch is coupled to said output lead of said master stage;
a slave stage having an input lead and an output lead, said input lead of said slave stage coupled to said output lead of said third switch, wherein said slave stage is capable of storing a logic value dependent on a logic state of said master-out signal provided by said master stage;
a fourth switch having a control lead, an input lead and an output lead, wherein said control lead of said fourth stage is adapted to receive said second clock signal, and said input lead of said fourth switch is coupled to said output lead of said third switch;
and
a first logic gate having an input lead coupled to said output lead of said fourth switch.

5 more elements

A computer system comprising:

a memory;
an interface capable of interfacing with one or more peripherals;
and a processor coupled to said memory and said interface, said processor including a circuit comprising:
a first switch having a control lead, an input lead and an output lead, wherein said control lead of said first switch is adapted to receive a first clock signal, and said input lead of said first switch is adapted to receive a first data signal;
a master stage having an input lead and an output lead, said input lead of said first stage coupled to said output lead of said first switch, wherein said master stage is capable of storing a logic value dependent on a logic state of a master-in signal received at said input lead of said master stage and of outputting a master-out signal at said output lead of said master stage having a logic state dependent on said logic value stored in said master stage;
a second switch having a control lead, an input lead and an output lead, wherein said control lead of said second switch is adapted to receive a second clock signal, said input lead of said second switch is adapted to receive a second data signal, and said output lead of said second switch is coupled to said input lead of said master stage;
a third switch having a control lead, an input lead and an output lead, wherein said control lead of said third switch is adapted to receive said first clock signal, and said input lead of said third switch is coupled to said output lead of said master stage;
a slave stage having an input lead and an output lead, said input lead of said slave stage coupled to said output lead of said third switch, wherein said slave stage is capable of storing a logic value dependent on a logic state of said master-out signal provided by said master stage;
a fourth switch having a control lead, an input lead and an output lead, wherein said control lead of said fourth stage is adapted to receive said second clock signal, and said input lead of said fourth switch is coupled to said output lead of said third switch;
and
a first logic gate having an input lead coupled to said output lead of said fourth switch.

8 more elements

Dependencies are inferred from the claim text.