Dead-time generating circuit
AssigneeSamsung Electronics Co., Ltd.
InventorSang-hyun Jin
Life of this patent
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Abstract
A dead-time generating circuit includes a first gate for generating a gate signal corresponding to a predetermined cutting width, and a second gate for cutting an input signal to be cut by the gate signal by the predetermined cutting width determined by a user and outputting the result. Therefore, an arbitrary block of a pulse width modulated (PWM) signal (whatever it may be in a logic "high" or "low") applied to the inverter of an AC servo driving circuit can be cut constantly by a predetermined cutting width. Also, the cutting width can be adjusted easily by the user.
Claims4
A circuit for stopping a normal response to an input signal by cutting-off said input signal for a predetermined time interval, said circuit comprising:
- a first gate means for generating a gate signal corresponding to said predetermined time interval determined by a user in response to said input signal and a control signal corresponding to said predetermined time interval;
- and
- a second gate means coupled to said input signal for cutting off said input signal by said predetermined time interval in response to said gate signal and outputting the result.
A dead-time generating circuit comprising:
- a first D-flipflop for receiving an input signal to be cut by a predetermined time interval at a clock port, receiving a logic "high" state at a preset port and a D-input port, and applying a first gate signal to a clear port, to output a second gate signal;
- an up/down counter for starting counting operation by the second gate signal, down-counting counted input values loaded to N data input ports by a predetermined clock signal to output counted output values, and outputting said first gate signal generated when the counted output values are 0;
- a means for discretionarily adjusting said counted input values corresponding to said time interval;
- and
- a second D-flipflop for receiving said first gate signal at a clock port, and receiving a logic "high" state at a D-input port and a clear port, and receiving a logic "high" state at a preset port, to output a signal obtained by cutting-off the input signal by said time interval.
Dependencies are inferred from the claim text.