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US 5,668,488 AGranted
Input buffer for a high density programmable logic device
AssigneeAdvanced Micro Devices, Inc.
InventorsBradley A. Sharpe-Geisler, Fabiano Fontana
Life of this patent
Estimating the term…
Abstract
An input buffer which provides compensation for the RC time delay introduced by a switch matrix of a high density programmable logic device (PLD). The input buffer includes circuitry to provide an input threshold which varies to compensate for the RC delay of the switch matrix to produce an output which transitions when a signal input to the switch matrix transitions through a predetermined value.
Claims22
A buffer having an input and an output, the input receiving a second data signal from delay circuit which forms the second data signal by introducing an RC delay in a first data signal, the buffer comprising:
- means for measuring a rate of change in voltage with respect to time (dV.sub.I dt) of the second data signal;
- and
- means for changing the threshold at the buffer input from a first threshold to a threshold having a value altered from the first threshold in proportion to a magnitude of the rate dV.sub.I /dt when the second signal changes states, so that the buffer output transitions at time intervals corresponding to when the first data signal transitions through a predetermined value.
A buffer having an input and an output, the buffer receiving a second data signal having a voltage changing at a rate with respect to time (dV.sub.I /dt) as the second data signal transitions between a first and a second state, the second data signal being received from a delay circuit which forms the second data signal by introducing RC delay in a first data signal, the buffer comprising:
- means for decreasing a threshold at the input of the buffer from a first threshold to a threshold having a value less than the first threshold in proportion to the rate dV.sub.I /dt when the voltage transitions form the first state to the second state;
- and
- means for increasing the threshold at the input of the buffer from the first threshold to a threshold having a value greater than the first threshold in proportion to the rate dV.sub.I /dt when the voltage transitions from the second state to the first state,
- wherein the means for increasing and the means for decreasing enable the buffer output to transition at time intervals corresponding to when the first data signal transitions through a predetermined value.
1 more element
A buffer comprising:
- a first inverter having an input and an output;
- a first n-channel transistor having a gate connected to the output of the first inverter and a source to drain path connecting an upper power supply (V.sub.DD) to a first node;
- a second n-channel transistor having a gate connected to the input of the first inverter and a source to drain path coupling the first node to a lower power supply (V.sub.SS);
- a third n-channel transistor having a source to drain path coupling the first node to the lower power supply (V.sub.SS), and having a gate;
- a first enabling transistor having a source to drain path coupling the gate of the third n-channel transistor to the input of the first inverter, and having a gate;
- a second enabling transistor having a source to drain path coupling the gate of the third n-channel transistor to the lower power supply (V.sub.SS), and having a gate;
- a pair of series inverters having an input connected to the first node and an output connected to the gate of the first enabling transistor;
- and
- a second inverter having an input connected to the output of the series inverters and an output connected to the gate of the second enabling transistor.
6 more elements
A buffer comprising:
- a first inverter having an input and an output;
- a pull up transistor having a gate connected to the input of the first inverter and a current path having a first end connected to the output of the first inverter and a second end;
- a pull up switching transistor having a gate and a current path having a first end connected to an upper power supply (V.sub.DD) and a second end connected to a second end of the current path of the pull up transistor;
- a pull down transistor having a gate connected to the input of the first inverter and a current path having a first end connected the output of the first inverter and a second end;
- and
- a pull down switching transistor having a gate and a current path having a first end connected to a lower power supply (V.sub.SS) and a second end connected to the second end of the current path of the pull down transistor;
- a second inverter having an input connected through a resistive element to the input of the first inverter and an output connected to the gate of the pull up switching transistor;
- and
- a third inverter having an input connected through a resistive element to the input of the first inverter and an output connected to the gate of the pull down switching transistor.
6 more elements
An input buffer for a programmable logic device, the input buffer having an input receiving a data signal from a switch matrix which introduces a given RC time delay in the data signal and an output, the input buffer comprising:
- a first inverter having an input forming the input of input buffer and an output;
- a pull up transistor having a gate connected to the input of the first inverter and a current path having a first end connected to the output of the first inverter and a second end;
- a pull up switching transistor having a gate and a current path having a first end connected to an upper power supply (V.sub.DD) and a second end connected to a second end of the current path of the pull up transistor;
- a pull down transistor having a gate connected to the input of the first inverter and a current path having a first end connected the output of the first inverter and a second end;
- a pull down switching transistor having a gate and a current path having a first end connected to a lower power supply (V.sub.SS) and a second end connected to the second end of the current path of the pull down transistor;
- a resistance transistor having a gate connected to the upper power supply (V.sub.DD) and a current path providing a resistance having a first end connected to the input of the first inverter and a second end;
- a second inverter having an input providing a parasitic capacitance and a threshold greater than a threshold of the first inverter and the maximum threshold of the first inverter combined with the pull up transistor, the input of the second inverter being connected to the second end of the current path of the resistance transistor, the second inverter having an output connected to the gate of the pull up switching transistor;
- and
- a third inverter having an input providing a parasitic capacitance and a threshold less than the threshold of the first inverter and the minimum threshold of the second inverter combined with the pull down transistor, the input of the third inverter being connected to the second end of the current path of the resistance transistor such that the parasitic capacitance at the input of the third inverter combined with the resistance proviced by the resistance transistor and parasitic capacitance of the second inverter provides an RC delay matching the given RC delay of the switch matrix, the third inverter having an output connected to the gate of the pull down switching transistor.
6 more elements
A buffer having an input and an output, the buffer comprising:
- a PMOS pull up transistor having a gate coupled to the buffer input, and a source to drain path coupling V.sub.DD to the buffer output;
- an NMOS pull down transistor having a gate coupled to the buffer input, and a source to drain path coupling the buffer output to V.sub.SS ;
- a second PMOS pull up transistor having a source to drain path coupling V.sub.DD to the buffer output, and having a gate forming a first node;
- a PMOS current source transistor having a source to drain path coupling V.sub.DD to the first node, and a gate connected to a first reference;
- an NMOS switching transistor having a source to drain path coupling the first node to the buffer input, and having a gate;
- and
- an NMOS pass transistor which is a depletion mode device, the NMOS pass transistor having a source to drain path coupling the buffer input to the gate of the NMOS switching transistor, and having a gate connected to a second reference.
4 more elements
A buffer having an input and an output, the buffer comprising:
- an inverter having an input coupled to the buffer input and an output coupled to the buffer output;
- and
- a pull up transistor having a source to drain path coupling VD.sub.DD to the buffer output, and having a gate forming a first node;
- a current source transistor having a source to drain path coupling V.sub.DD to the first node, and a gate connected to a reference;
- a switching transistor having a source to drain path coupling the first node to the buffer input, and having a gate;
- and
- a pass transistor having a source to drain path coupling the buffer input to the gate of the switching transistor, and having a gate connected to a reference.
4 more elements
Dependencies are inferred from the claim text.