High frequency clock signal distribution circuit with reduced clock skew
AssigneeNEC Corporation
InventorMasahiro Nomura
Life of this patent
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Abstract
A clock signal distribution circuit of a tree structure having a plurality of buffers arranged in a plurality of hierarchical stages includes short-circuit wirings for short-circuiting output terminals of the buffers at each stage of the plurality of hierarchical stages. Each of the plurality of buffers is formed by a single inverter or a multi-stage inverter wherein an input stage inverter and an output stage inverter are connected in series. The output stage inverter has a size larger than that of the input stage inverter. The clock signal distribution circuit thus constructed can reduce clock skew and distribute a high frequency clock signal having sharp rise and fall characteristics to a plurality of registers.
Claims11
A clock signal distribution circuit having an H-tree structure, said distribution circuit comprising:
- a plurality of buffers arranged in a plurality of hierarchical stages, in an H-tree structure;
- and short-circuit wirings for short circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages.
A clock signal distribution circuit having an H-tree structure wherein a plurality of buffers are arranged in a plurality of hierarchical stages with the same load and the same wiring length, said clock signal distribution circuit comprising:
- a combination of an input stage inverter and an output stage inverter comprising each of said plurality of buffers, said output stage inverter being connected in series to said input stage inverter and formed by a transistor larger in size than that of said input stage inverter so that each of said plurality of buffers has a low output on-resistance and a small input capacitance;
- and
- a short-circuit wiring for short-circuiting output terminals of said buffers at each stage of said plurality of hierarchical stages in said H-tree structure.
A clock signal distribution circuit of a tree structure, having a plurality of hierarchical stages, each of said hierarchical stages comprising:
- n buffers, where n is an integer from 1 to N, each of said n buffers comprising:
- at least one inverter;
- an input stage for supplying a clock signal to said at least one inverter;
- an output stage, for outputting the clock signal from said at least one inverter, said output stage connected in series to an input stage of a next one of said hierarchical stages;
- and
- a short circuit wire connecting said output stage at each hierarchical level.
A reduced skew H-tree clock signal distribution circuit having a plurality of hierarchical stages, comprising:
- a first stage comprising a buffer, said buffer comprising an input for receiving a clock signal and an output for outputting the clock signal;
- wiring connected to said output of said first stage, said wiring arranged in an H-tree pattern having four connection points;
- a second stage, connected to one of said four connection points, said second stage comprising four buffers each comprising and input stage for receiving the clock signal from said first stage, and an output for outputting the clock signal;
- and
- a short-circuit wire electrically connecting together the output of each of said buffers of said second stage.
Dependencies are inferred from the claim text.