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US 5,668,399 AGranted
Semiconductor device with increased on chip decoupling capacitance
AssigneeInternational Business Machines Corporation
InventorsJohn Edward Cronin, John Andrew Hiltebeitel
Life of this patent
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Abstract
A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.
Claims10
A decoupling capacitor of a semiconductor device, comprising:
- a vertically-defined capacitor comprising a first layer of metallurgy separated by a dielectric layer:
- said first layer of metallurgy being located above a surface of said semiconductor device
- said dielectric layer being located on top of and aligned with said first layer of metallurgy, relative to said surface of said semiconductor device;
- said second layer of metallurgy being located on top of and aligned with said dielectric layer, relative to said surface of said semiconductor device;
- and
- wherein said vertically-defined capacitor is self-aligned about its perimeter with said first and second layers of metallurgy and of said dielectric layer being self-aligned and patterned together in one step.
3 more elements
A decoupling capacitor of a semiconductor device, comprising:
- a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer;
- said first layer of metallurgy being located on a surface of said semiconductor device;
- said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device;
- said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device;
- portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being co-aligned and patterned together in one step;
- wherein said first layer of metallurgy is disposed over a first lower level of connection of the semiconductor device for electrical coupling thereto;
- and
- wherein said second layer of metallurgy is electrically coupled to a second lower level of connection of the semiconductor device via a third metallurgy layer disposed over the second lower level connection, the third metallurgy layer and second lower level of connection being adjacent to said first and second layers of metallurgy.
5 more elements
A decoupling capacitor of a semiconductor device, comprising:
- a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer;
- said first layer of metallurgy being located on a surface of said semiconductor device;
- said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device;
- said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device;
- portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step;
- and
- wherein said first and second layers of metallurgy have an opening disposed over a lower level of connection of the semiconductor device and said second layer of the two layers of metallurgy is electrically coupled to the lower level of connection by way of metallurgy filling the opening.
4 more elements
A decoupling capacitor of a semiconductor device, comprising:
- a first layer of metallurgy and a second layer of metallurgy separated by a dielectric layer;
- said first layer of metallurgy being located on a surface of said semiconductor device;
- said dielectric layer being located on top of said first layer of metallurgy, relative to said surface of said semiconductor device;
- said second layer of metallurgy being located on top of said dielectric layer, relative to said surface of said semiconductor device;
- portions of perimeters of said first and second layers of metallurgy and of said dielectric layer being coaligned and patterned together in one step;
- and
- wherein said second layer of the two layers of metallurgy and the dielectric layer therebetween include an opening lined with insulating passivation material, metallurgy being deposited through the opening for establishing an electrical contact coupled to said first layer of the two layers of metallurgy.
4 more elements
Dependencies are inferred from the claim text.