Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance

A reduced area self-aligned metal contact to a thin polysilicon layer contiguous with and forming a portion of a thin film transistor on a semiconductor substrate, comprising the steps of:

• a semiconductor substrate having semiconductor devices formed from patterned first and second polysilicon layers and having a first insulating layer there between, and a separate portion of said second polysilicon layer forming also a buffer layer;
• a second insulating layer on said buffer layer and on said substrate;
• a patterned third polysilicon layer forming a gate electrode for said thin film transistor;
• a third insulating layer on said patterned third polysilicon layer and forming a gate oxide on said gate electrode and said gate oxide extending over said buffer layer;
• a patterned thin fourth polysilicon layer over said third insulating layer doped selectively to form source and drain area for said thin film transistor, and said patterned thin fourth polysilicon layer formed to provide doped electrically conducting stripe contiguous with one of said source and drain areas and extending over said buffer layer;
• a fourth insulating layer over said patterned fourth polysilicon layer;
• said fourth insulating layer having a contact opening to said buffer layer with portions of sidewall formed from said thin fourth polysilicon layer;
• a patterned first metal layer over said fourth insulating layer and in said contact opening, and making low resistance ohmic contact to said fourth polysilicon layer, and thereby having a reduced area self-aligned metal contact to said thin fourth polysilicon layer contiguous with said one of said source and drain areas of said thin film transistor, said first metal layer connects to a power supply.