US 5,668,027 AGranted

Method of manufacturing a MOS transistor semiconductor device

AssigneeNippon Steel Semiconductor Corporation

InventorMasayuki Hashimoto

Life of this patent

Estimating the term…

Loading patent…

Abstract

A MOS transistor semiconductor device has a gate electrode portion with a spacer film, diffused regions diffused with dopants, and element-separating regions. After the formation of the gate on the substrate, a spacer oxide is formed adjacent to the gate. A polysilicon layer doped with the same dopants as the diffused regions is formed between the element-separating regions and the spacer film. The polysilicon layer is overlaps portions of the gate electrode and the element-separating regions that are close to the diffused regions. Thermal diffusion of the dopants from the polysilicon layer to the substrate is performed to further dope the diffused regions. After an insulation layer is formed over the polysilicon layer, connection holes are formed through the insulation layer to connect the polysilicon layer to metal interconnects. In this MOS transistor, the polysilicon layer provides holes that are larger in diameter than holes at the openings of the diffused regions that are part of the substrate surface. Therefore, the area on the silicon substrate surface occupied by diffused layers is reduced to permit semiconductor elements to be packed at a high density. The resistances of interconnects are also suppressed.

Claims25

Dependent claims

A method of manufacturing a MOS transistor semiconductor device having a gate electrode portion, dopant-diffused regions, and circuit element-separating regions, the gate electrode portion having a spacer-insulating film, a gate polysilicon layer and a gate cap oxide film formed on the gate polysilicon layer, said method comprising the steps of:

forming the gate electrode portion of the MOS transistor semiconductor device and the circuit element-separating regions on a substrate surface of a silicon substrate, a separation region at the substrate surface separating the gate electrode portion and the circuit element-separating regions;
depositing a polysilicon layer and doping the polysilicon layer with dopants onto the gate electrode portion, the separation region, and the circuit element-separating regions, the polysilicon becoming part of the dopant-diffused regions at the separation region;
patterning and removing the polysilicon layer after doping the layer from portions of the gate electrode portion and the circuit element-separating regions, the polysilicon layer remaining in the dopant-diffused regions and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region;
depositing an insulating film on the semiconductor device;
thermally treating the semiconductor device to diffuse the dopants into the substrate surface in contact with the polysilicon layer, the polysilicon layer being a diffusant source to form diffused regions at the substrate surface, the step of thermally treating planarizes the surface of the semiconductor device;
removing the insulating film on a part of the polysilicon layer to form connection holes;
and
forming conductive interconnects in the connection holes.

5 more elements

A method of manufacturing NMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of:

forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface;
forming a gate oxide cap film on the gate electrode portion;
implanting a first dopant into the exposed portion of the substrate surface;
forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface;
depositing a polysilicon layer on the NMOS transistor;
implanting a second dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer;
removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region;
depositing an insulating film on the NMOS transistor;
thermally treating the NMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer;
forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions;
and
forming conductive interconnects in the connection holes.

9 more elements

A method of manufacturing PMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of:

forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface;
forming a gate oxide cap film on the gate electrode portion;
forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface;
depositing a polysilicon layer on the PMOS transistor;
implanting a dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer;
removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region;
depositing an insulating film on the PMOS transistor;
thermally treating the PMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer;
forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions;
and
forming conductive interconnects in the connection holes.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/268,325Filed 30 Jun 1994 · division
Priority: JP 3-29630616 Oct 1991
Granted: 16 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10P 32/171
Characterised by the semiconductor material: being group IV material
H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs