Process for fabricating a semiconductor device having a segmented channel region
AssigneeMotorola, Inc.
InventorsChitra K. Subramanian, James D. Hayden
Life of this patent
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Abstract
A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).
Claims11
A process for fabricating a semiconductor device comprising the steps of:
- providing a semiconductor substrate having a dielectric layer thereon;
- forming a first polycrystalline silicon layer overlying the dielectric layer;
- forming an insulating layer overlying a first portion and a second portion of the first polycrystalline silicon layer;
- forming an opening in the insulating layer exposing the first portion of the first polycrystalline silicon layer, the opening having a wall surface;
- forming a first sidewall spacer adjacent to the wall surface;
- forming a buried junction region in the semiconductor substrate aligned to the first sidewall spacer;
- filling the opening with a second polycrystalline silicon layer;
- removing the insulating layer and the second portion of the first polycrystalline silicon layer;
- forming a second sidewall spacer adjacent to the first sidewall spacer and overlying the dielectric layer;
- and
- forming source and drain regions in the semiconductor substrate.
A process for fabricating a semiconductor device comprising the steps of:
- providing a semiconductor substrate having a first polycrystalline silicon layer overlying the semiconductor substrate and separated therefrom by a dielectric layer;
- forming an insulating layer overlying the first polycrystalline silicon layer;
- forming an opening in the insulating layer to define a gate region in the first polycrystalline silicon layer and leaving a remaining portion of the first polycrystalline silicon layer covered by the insulating layer, the opening having a wall surface;
- forming a first sidewall spacer in the opening adjacent to the wall surface;
- implanting dopants into the semiconductor substrate to form a buried junction region in the semiconductor substrate using the first sidewall spacer as a doping mask;
- filling the opening with a second polycrystalline silicon layer;
- removing the insulating layer and the remaining portion of the first polycrystalline silicon layer;
- forming a second sidewall spacer adjacent to the gate region and to the first sidewall spacer;
- and
- forming source and drain regions in the semiconductor substrate.
A process for fabricating a semiconductor device comprising the steps of:
- providing a semiconductor substrate of a first conductivity type having a first polycrystalline silicon layer overlying the semiconductor substrate and separated therefrom by a dielectric layer;
- implanting the semiconductor substrate to form a surface channel region of the first conductivity type therein;
- forming an insulating layer overlying the first polycrystalline silicon layer;
- forming an opening in the insulating layer to define a gate region in the first polycrystalline silicon layer and leaving a remaining portion of the first polycrystalline silicon layer covered by the insulating layer, the opening having a wall surface;
- forming a first sidewall spacer in the opening adjacent to the wall surface;
- implanting dopants of a second conductivity type into the substrate to form a buried junction region in the substrate using the first sidewall spacer as a doping mask;
- filling the opening with a second polycrystalline silicon layer of the second conductivity type;
- filling the opening with a second polycrystalline silicon layer;
- removing the insulating layer and the remaining portion of the first polycrystalline silicon layer;
- forming a second sidewall spacer adjacent to the gate region and to the first sidewall spacer;
- and
- implanting dopants of the second conductivity type into the semiconductor substrate to form source and drain regions using the second sidewall spacer as a doping mask.
Dependencies are inferred from the claim text.