Phase-locked loop timing controller in an integrated circuit memory
AssigneeNEC Electronics Corporation
InventorCecil W. Conkle
Life of this patent
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Abstract
Interleaved operation of multiple memory banks is improved by including a frequency multiplier and a synchronizing circuit, such as a phase-locked loop, as part of an integrated circuit memory chip. Frequency multiplication supplies additional clock edges for timing different phases of the system clock signal. The synchronizing circuit provide precise control of clock edge timing to exactly align the timing signals in one memory chip with the timing signals in another memory chip despite variability in temperature, process and voltage parameters between the chips.
Claims31
An integrated circuit memory comprising:
- memory array;
- and
- a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including:
- a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
A computer system comprising:
- a memory controller;
- a data bus coupled to the memory controller;
- and
- a plurality of memory banks coupled to the data bus and mutually sharing data bus access, each of the plurality of memory banks being an integrated circuit memory including:
- a memory array;
- and
- a timing circuit coupled to the memory array via an internal clock line and coupled to an external signal clock line, the timing circuit including:
- a clock multiplier and clock edge synchronizing circuit having an input terminal coupled to the external signal clock line and having an output terminal coupled to the internal clock line, wherein the clock multiplier and clock edge synchronizing circuit multiplies a timing signal provided on the external clock line.
A method of operating a plurality of memory banks comprising the steps of:
- receiving a clock signal at a clock frequency;
- multiplying the clock frequency to generate multiple clock edges;
- timing a plurality of phases of the clock signal with the clock edges;
- synchronizing timing of the multiple clock edges;
- and
- driving a plurality of memory banks, each memory bank being driven with selected individual clock edge of the multiple clock edges.
Dependencies are inferred from the claim text.