Method and apparatus for designing an integrated circuit

A method for making a plurality of integrated circuits, the method comprising the steps of:

• providing a behavior model representing the functional operation of each of the integrated circuits in the plurality of integrated circuits;
• providing an initial library of logic cells;
• using the logic cells of the initial library and the functional operation within the behavioral model to generate a logic gate representation of each of the integrated circuits in the plurality of integrated circuits;
• modifying the logic gate representation to generate a new logic gate representation;
• generating a new library of logic cells from the contents of the new logic gate representation;
• generating a physical design file from the new library of logic cells, the physical design file being a description of a physical integrated circuit having substantially the functional operation of the behavioral model;
• and
• making the plurality of integrated circuits in accordance with the physical design file.

A design generator for generating an integrated circuit file which contains data which allows an integrated circuit to be manufactured, the design generator comprising:

• means for receiving cell data from a predetermined library which contains a predetermined plurality of logic cells;
• means for receiving behavioral data from a behavior model which comprises a logical description of the functionality of the integrated circuit;
• means for using the behavior data and the cell data to generate a gate schematic net list of the integrated circuit where the gate schematic net list contains the cell data;
• means for altering the cell data within the gate schematic net list to create hybrid cell data within the gate schematic net list in order to optimize the gate schematic net list;
• means for creating a new library of logic cells from the hybrid cell data within the gate schematic net list;
• and
• means for using the new library to generate the integrated circuit file in accordance with the gate schematic net list.

A design generator for generating an integrated circuit file for an integrated circuit, the design generator being stored via storage media and comprising:

• a first storage region within the storage media for storing a first plurality of binary values, the first plurality of binary values controlling receipt of cell data from a predetermined library which contains a predetermined plurality of logic cells;
• a second storage region within the storage media for storing a second plurality of binary values, the second plurality of binary values controlling receipt of behavioral data from a behavior model which comprises a logical description of the functionality of the integrated circuit;
• a third storage region within the storage media for storing a third plurality of binary values, the third plurality of binary values controlling a use of the behavior data and the cell data to generate a gate schematic net list of the integrated circuit where the gate schematic net list contains the cell data;
• a fourth storage region within the storage media for storing a fourth plurality of binary values, the fourth plurality of binary values controlling an altering of the cell data within the gate schematic net list to create hybrid cell data within the gate schematic net list in order to optimize the gate schematic net list;
• and
• a fifth storage region within the storage media for storing a fifth plurality of binary values, the fifth plurality of binary values allowing creation of a new library of logic cells from the hybrid cell data within the gate schematic net list and using this new library of logic cells to generate the integrated circuit file in accordance with the behavioral model.

A method for creating a library of logic cells, the method comprising the steps of:

• scanning a gate netlist of an integrated circuit to determine a plurality of logic gates needed within the library of logic cells;
• placing and routing each logic gate in the plurality of logic gates to form a plurality of logic cells, the placing and routing performed automatically by place and route automated process;
• logically verifying each logic cell in the plurality of logic cells to ensure that the logic cells in the plurality of logic cells are logically equivalent to corresponding logic gates in the plurality of logic gates, the logically verifying being performed by an automated verification process;
• verifying design rule constraints of each logic cell in the plurality of logic cells via an automated design rule checker;
• extracting parasitic parameters from each logic cell in the plurality of logic cells via an automated parameter extractor;
• extracting characterization data from each logic cell in the plurality of logic cells, the extracting being performed via an automated characterization process;
• and
• placing and routing the plurality of logic cells from the library of logic cells in accordance with the gate netlist to create a layout file.

A method for determining logic cell boundaries when provided with a behavioral model of an integrated circuit, the method comprising the steps of:

• providing the behavioral model containing a first logic library cell and a second logic library cell, the first logic library cell comprising a first logic gate and a second logic gate while the second logic library cell comprises a third logic gate where the first, second, and third logic gates are physically separated logic gates;
• creating a new library of logic cells from the behavioral model wherein the new library contains a first hybrid logic cell that comprises the first logic gate and a second hybrid logic cell that comprises the second and third logic gate;
• and
• using the new library of logic cells to create a two-dimensional data file of the integrated circuit containing the first and second hybrid logic cells to respectively replace the first and second logic library cells.

A method for placing a circuit on an integrated circuit layout, the method comprising the steps of:

• generating a net list from a logic cell library and a behavioral circuit model, wherein the behavioral circuit model defines functionality of the circuit;
• redefining a boundary of at least one logic cell of the logic cell library based on the net list and logic cell coupling to produce a redefined logic cell library;
• and
• placing the circuit in a two-dimensional layout based on the net list and the redefined logic cell library.