US 5,665,642 AGranted

Process of making a semiconductor device with a multilayer wiring and pillar formation

AssigneeSony Corporation

InventorKatsuyuki Kato

Life of this patent

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Abstract

A method of manufacturing semiconductor interconnection includes the steps of providing a bottom conductive layer having an auxiliary conductive layer applied on top of the bottom conductive layer. The auxiliary conductive layer is patterned and subsequently a further conductive layer is applied over the patterned auxiliary conductive layer. A mask is then applied over the further conductive layer to form a pillar connection which provides a reliable connection in a semiconductor device.

Claims8

Dependent claims

A process for producing a semiconductor device comprising:

forming a bottom conductive layer;
forming an auxiliary conductive layer on the bottom conductive layer;
patterning just the auxiliary conductive layer formed on the bottom conductive layer thereby forming a first pattern of the auxiliary conductive layer;
forming a pillar conductive layer on the first pattern of the auxiliary conductive layer, the first pattern of the auxiliary conductive layer having a top surface, an edge and a side surface;
patterning the pillar conductive layer with a second pattern corresponding to a pattern of connection having a region overlapping the top surface of the first pattern of the auxiliary conductive layer and a region extending over the edge of the first pattern of the auxiliary conductive layer and covering the side surface of the first pattern of the auxiliary conductive layer thus forming a second pattern of a pillar connection portion;
and
etching the bottom conductive layer with an etching mask defined by the second pattern of the pillar connection portion and the first pattern of the auxiliary conductive layer to pattern the bottom conductive layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/444,288Filed 18 May 1995 · division
Priority: JP 5-10476630 Apr 1993
Granted: 9 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material
H10W 20/0633
By forming conductive members before forming protective insulating material: using subtractive patterning of the conductive members
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias

Family

Serial233,997Parent of this division · filed 28 Apr 1994
US 5,554,888 AParent of this division
US 5,665,642 AThis patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

Facts

Application

08/444,288Filed 18 May 1995 · division

Priority

JP 5-10476630 Apr 1993

Granted

9 Sep 1997

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material
H10W 20/0633
By forming conductive members before forming protective insulating material: using subtractive patterning of the conductive members
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias