US 5,665,615 AGranted

Method of making BiCMOS semiconductor device

AssigneeSony Corporation

InventorHiroaki Anmo

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Abstract

A BiCMOS semiconductor device comprising a substrate, a vertical bipolar transistor provided on the substrate and having a first conductive base terminal electrode formed in a portion of a first semiconductor film provided on the substrate, a second conductive semiconductor terminal electrode formed in a second semiconductor film provided through an insulating layer on the first semiconductor film, the first and second conductive electrodes being disposed such that portions thereof overlap each other, and an LDD (lightly doped drain)-type MOS transistor provided on the substrate and having a gate electrode formed in a portion of said first semiconductor film and a gate side wall formed on a side wall of said gate electrode, wherein the insulating layer is caused to exist selectively in a region in which the first and second conductive electrodes are overlapped, and constitutes at least a portion of the gate side wall.

Claims6

Dependent claims

A method of manufacturing a BiCMOS semiconductor device comprising a substrate, a vertical bipolar transistor and an LDD (lightly doped drain)-type MOS transistor, the latter two being both provided on said substrate, said method comprising the steps of:

(1) forming a first semiconductor film on said substrate and subjecting said first semiconductor film to a patterning to form a first conductive base terminal electrode of said vertical bipolar transistor and a gate electrode of said LDD-type MOS transistor;
(2) subjecting said substrate to low-concentration ion-implantation in which said gate electrode is used as a mask to form an LDD region of said LDD-type MOS transistor;
(3) covering an entire surface of said substrate with an insulating layer;
(4) forming an emitter window to expose said substrate by subjecting each of said insulating layer and said base terminal electrode to a patterning simultaneously;
(5) forming an insulating emitter side wall on an inner side surface of said emitter window;
(6) depositing a second semiconductor film on an entire surface of said substrate;
(7) subjecting said second semiconductor film to a patterning to form a second conductive emitter terminal electrode;
(8) subjecting said insulating layer to an etch back process by using said emitter terminal electrode as a mask to expose at least an upper surface of said gate electrode, a portion of said base terminal electrode and an active region of said substrate and form a gate side wall on a side surface of said gate electrode;
and
(9) subjecting said substrate to a high-concentration ion-implantation in which said gate electrode and said gate side wall are used as a mask to form drain/source regions of said LDD-type MOS transistor.

7 more elements

(1) forming a first semiconductor film on said substrate and subjecting said first semiconductor film to a patterning to form a first conductive base terminal electrode of said vertical bipolar transistor and a gate electrode of said LDD-type MOS transistor;
(2) subjecting said substrate to a low-concentration ion-implantation in which said gate electrode is used as a mask, to form an LDD region of said LDD-type MOS transistor;
(3) covering an entire surface of said substrate with a first insulating layer;
(4) etching back said first insulating layer to form an inner gate side wall layer on a side surface of said gate electrode;
(5) subjecting said substrate to a high-concentration ion-implantation in which said gate electrode and said inner gate side wall layer are used as a mask to form drain/source regions of said LDD-type MOS transistor;
(6) covering the entire surface of said substrate with a second insulating layer;
(7) forming an emitter window to expose said substrate by subjecting said second insulating layer and said base terminal electrode to a patterning simultaneously;
(8) forming an insulating emitter side wall on an inner wall surface of said emitter window;
(9) depositing a second semiconductor film on the entire surface of said substrate;
(10) subjecting said second semiconductor film to a patterning to form a second conductive emitter terminal electrode;
and
(11) etching back said second insulating layer by using said emitter terminal electrode as a mask to expose at least an upper surface of said gate electrode, a portion of said base terminal electrode and an active region of said substrate and form an outer gate side wall layer on a surface of said inner gate side wall layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/600,539Filed 13 Feb 1996
Priority: JP 7-02521914 Feb 1995
Granted: 9 Sep 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 84/401
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by…
H10D 84/0109
Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00,…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS