High removal rate chemical-mechanical polishing

#The present invention relates to a method and apparatus for chemical-mechanical polishing (CMP), particularly for planarizing an insulating layer.

#Semiconductor integrated circuits are typically manufactured by forming an array of separate dies on a common semiconductor wafer. During processing, the semiconductor wafer is treated to form specified regions of insulating, conductive and semiconductor type materials. The ever increasing requirements for high density devices comprising conductive wiring patterns with increasingly smaller distances between conductive lines and small diameter vias in dielectric layers, particularly at high rates of production, pose a significant technological challenge. Conventionally, a conductive wiring pattern comprising a dense array of conductive lines is formed by depositing a metal layer, etching to form a conductive pattern and applying a dielectric material. Single and dual damascene techniques have also been employed to form openings in a dielectric layer which are subsequently filled with metal. The application of damascene techniques to the manufacture of semiconductor devices is disclosed in Joshi, "A New Damascene Structure for Submicrometer Interconnect Wiring," IEEE Electron Letters, Vol. 14, No. 3, Mar. 1993, pp. 129-132; Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," Jun. 11-12, 1991, VMIC Conference, IEEE, pp. 144-152; Kenney et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM," 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 14-15; U.S. Pat. Nos. 5,262,354; and 5,093,279. After formation of the wiring pattern, planarization is effected as by chemical-mechanical polishing.

#As shown in FIG. 1A, during an initial processing stage for forming an integrated circuit, a dielectric film 10 is deposited over a patterned conductive layer such as a metal 11. The object is to planarize steps 12 in dielectric layer 10 as shown in FIG. 1B. After deposition of layer 10, the portion thereof outside the trench must be removed. Such removal can be effected by plasma etching, or by a simplified faster and relatively inexpensive method known as chemical-mechanical planarization or polishing (CMP).

#FIG. 1A schematically illustrates a covered pattern prior to planarization.

#FIG. 1B schematically illustrates a planarized pattern.

#FIG. 2 schematically illustrates a typical CMP apparatus.

#The following examples demonstrate the effectiveness of the present invention.

#Semiconductor wafers were provided with a dielectric layer of silicon dioxide derived from deposited TEOS in a conventional manner. Some dielectric layers were nndoped and others doped with boron and phosphorous. The polishing pad employed was IC 1000 over SUBA IV marketed by Rodel Corporation, Newark, Del. Table II sets forth the CMP parameters employed.

#TABLE II ______________________________________ Undoped oxides Doped oxides ______________________________________ Polish arm PRESSURE = 10 psi 10 psi Wafer carrier Speed = 10 rpm 15 rpm Polish Pad Rotation = 65 rpm 20-65 rpm Slurry flow = 100-200 ml/min 100-200 ml/min Slurry Conditions = Ambient Ambient ______________________________________