Checksum generation circuit and method

A checksum generator for generating an N bit checksum from data provided on first and second N bit data inputs, comprising:

• a first adder for summing two N bit operands, an output of the first adder being coupled to feedback an N bit sum result to a first input of the first adder, a carry-out of the first adder being coupled to feedback a carry bit to a carry-in of the first adder, and a second input of the first adder being coupled to receive data from said first N bit data input;
• and
• a second adder for summing two N bit operands, an output of the second adder being coupled to feedback an N bit sum result to a first input of the second adder, a carry-out of the second adder being coupled to feedback a carry bit to a carry-in of the second adder, and a second input of the second adder being coupled to receive data from said second N bit data input;
• wherein the output of the second adder and the carry-out of the second adder are multiplexed with said first N bit data input to the second input of the first adder.

A checksum generator circuit for generating a checksum from a stream of data values, comprising:

• a first binary adder having first and second adder inputs, a first sum output, a first carry-output and a first carry input, said first carry-output being coupled to said first carry input;
• a second binary adder having third and fourth adder inputs, a second sum output, a second carry-output and a second carry input, said second carry-output being coupled to said second carry input;
• a first register coupled to said first sum output and said first adder input;
• a second register coupled to said second sum output and said third adder input;
• and
• a multiplexer having an output coupled to said second adder input, and having inputs coupled to receive a first data input, and coupled to said second register and said second carry-output;
• said fourth adder input being coupled to receive a second data input.

A method for generating a checksum from a pair of first and second data streams, comprising the steps of:

• synchronously summing the first and second data streams in a series of summing cycles, at each summing cycle utilizing a carry-out value from a preceding summing cycle as a carry-in value, so as to generate first and second sums having first and second carry-out values;
• adding said first and second sums with said first carry-out value, so as to generate a third sum having a third carry-out value;
• adding said second and third carry-out values to said third sum, so as to generate a fourth sum having a fourth carry-out value;
• and
• adding said fourth carry-out value is added to said fourth sum so as to generate a checksum for the data contained in the first and second data streams.

A data transmission interface for coupling a host computer for communication through an asynchronous transfer mode (ATM) telecommunications network, comprising:

• a load engine coupled to retrieve a packet of data from said host computer;
• a segmentation engine for segmenting said data packet into cells and passing the cells of data to said ATM network;
• and
• a checksum generator coupled to receive said data packet from said load engine, and for generating a checksum value from said data packet to be passed to said ATM network by way of said segmentation engine, said checksum generator comprising:
• a first adder having first and second adder inputs, a first sum output, and having a first carry-out coupled to feedback a first generated carry bit to a carry-in of the first adder, said first adder input being coupled to receive first input data from said load engine, and said first sum output being coupled to feedback first partial sum data to said second adder input;
• and
• a second adder having third and fourth adder inputs, a second sum output, and having a second carry-out coupled to feedback a second generated carry bit to a carry-in of the second adder, said second sum output being coupled to feedback second partial sum data to said third adder input, and wherein said fourth adder input is coupled to said first adder to selectively receive second input data from said load engine, said first partial sum data from said first sum output, and said first generated carry bit from said first carry-out.