Series terminated clock deskewing apparatus

A circuit comprising a plurality of series terminated clock deskewing apparatuses and a corresponding plurality of loads, wherein each load is coupled to one of the plurality of series terminated clock deskewing apparatuses for delivering a clock signal input to each of the corresponding plurality of loads and each of the series clock deskewing apparatuses delays the clock signal input a different amount of time so that the clock signal input is received by all loads simultaneously, each of the plurality of series terminated clock deskewing apparatuses comprising:

• a. means for delay coupled to the clock signal input and having a first time delay;
• and
• b. a variable delay loop coupled to the clock signal input and a load, the variable delay loop including:
• i. a first variable delay line coupled to the clock signal input and having a second time delay;
• ii. series means for transmitting the clock signal input to the load and for receiving a reflected signal representative of the clock signal input from the load, wherein the series means is coupled to the first variable delay line and the load and having a third time delay, wherein the third time delay is representative of a round trip delay;
• iii. a second variable delay line coupled to the series means for transmitting and having a fourth time delay;
• and
• iv. means for synchronizing and filtering the clock input signal coupled to the means for delay, the first variable delay line and the second variable delay line;
• wherein the means for synchronizing and filtering matches the first time delay to the sum of the second, third, and fourth time delays by varying the second time delay and the fourth time delay.

A series terminated clock deskewing apparatus for delivering a clock signal input to a load, comprising:

• a. a maximum delay line having an input and an output, the input of the maximum delay line coupled to the clock signal input;
• b. a first variable delay line having an input and an output, the input of the first variable delay line coupled to the clock signal input;
• c. an output driver having an input and an output, the input of the output driver coupled to the output of the first variable delay line;
• d. a series resistor having a first terminal and a second terminal, the first terminal of the series resistor coupled to the output of the output driver;
• e. a transmission line having a characteristic impedance coupled between the second terminal of the series resistor and a load;
• f. a divider having an input and an output, the input of the divider coupled to the output of the output buffer and the first terminal of the series resistor;
• g. a subtractor having a first input, a second input and an output, the first input of the subtractor coupled to the second terminal of the series resistor and the transmission line, the second input of the subtractor coupled to the output of the divider, the subtractor for outputting the difference between a value at the second terminal of the series resistance and a value at the output of the divider;
• h. an input buffer having an input and an output, the input of the input buffer coupled to the output of the subtractor;
• i. a second variable delay line having an input and an output, the input of the second variable delay line coupled to the output of the input buffer;
• j. a phase detector having a first input, a second input and an output, the first input of the phase detector coupled to the output of the maximum delay line and the second input of the phase detector coupled to the output of the second variable delay line, the phase detector for synchronizing the output of the maximum delay line and the output of the second variable delay line;
• and
• k. a low-pass filter having an input and an output, the input of the low-pass filter coupled to the output of the phase detector, the output of the low-pass filter coupled to control the operation of the first variable delay line and the second variable delay line, the low-pass filter for smoothing the output of the phase detector.

A circuit comprising a plurality of series terminated clock deskewing apparatuses and a corresponding plurality of loads, wherein each load is coupled to one of the plurality of series terminated clock deskewing apparatuses for delivering a clock signal input to a corresponding each of the plurality of loads and each of the series clock deskewing apparatuses delays the clock signal input an appropriate amount of time so that the clock signal input is received by all loads simultaneously, each of the plurality of series terminated clock deskewing apparatuses comprising:

• a means for delay coupled to the clock signal input and having a first time delay;
• and
• b. a variable delay loop coupled to the clock signal input and to a corresponding one of the plurality of loads, the variable delay loop including:
• i. a first variable delay line coupled to the clock signal input and having a second time delay;
• ii. series means for transmitting a signal representative of the clock signal to the load and for receiving a reflected signal from the load, wherein the series means is coupled to the first variable delay line and to the corresponding load and has a third time delay representative of a round trip delay time from when the signal representative of the clock signal is transmitted and when the reflected signal is received;
• iii. a second variable delay line coupled to the series means for transmitting and having a fourth time delay;
• and
• iv. means for ensuring that each of the loads receives the corresponding signal representative of the clock signal at substantially the same time, wherein the means for ensuring is coupled to control the second and fourth time delay.