US 5,661,419 A · Dynamic phase-frequency detector circuit

Abstract

A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck. These features make the detector desirable for use in VLSI clock regeneration circuits where high operating frequencies and tight layout restrictions place a premium on circuit size and performance.

Claims19

Dependent claims

A sequential phase-frequency detector having REFERENCE and LOCAL inputs and UP and DOWN outputs, the detector including a first pulse generator triggered on the rising edge of the LOCAL input for resetting the UP output and for permitting the assertion of the UP output when the LOCAL input is stuck at a high level.

A method for comparing two digital input signals and for turning ON one of two digital output signals based upon which input signal includes a first occurrence of a predetermined feature and turning OFF said one output signal at a next occurrence of said feature in the other input signal, such that an ON duration of the one output signal is proportional to a time interval between said first and next occurrences of the predetermined feature, the method comprising the steps of:

providing the two digital input signals, and defining one input signal as a REFERENCE input and the other input signal as a LOCAL input;
providing means for generating two digital output signals, and defining one output signal as an UP signal and the other output signal as a DOWN signal;
providing a two-state sequential machine connected for determining a first and a next occurrence of the predetermined feature;
responding to a first occurrence of the predetermined feature on the REFERENCE input by turning ON the UP output signal independent of the LOCAL input;
providing a pulse generator connected for turning OFF the UP output signal, and triggered at an occurrence of the predetermined feature of the LOCAL input;
responding to an occurrence of the predetermined feature on the LOCAL input by triggering the pulse generator, thereby turning OFF the UP output signal;
responding to a first occurrence of the predetermined feature on the LOCAL input by turning ON the DOWN output signal;
and
responding to a next occurrence of the predetermined feature on the REFERENCE input by turning OFF the DOWN output signal.

6 more elements

A CMOS clock regeneration system for providing multi-phase clock output signals locked to the frequency and phase of an input clock REFERENCE signal, having a signal interval, the clock regeneration system comprising:

a voltage-controlled delay line having an input for receiving the REFERENCE signal, a digital output corresponding to a fully delayed REFERENCE signal, an analog control voltage input line for adjusting the duration of the full delay in proportion to the analog Control voltage, and a plurality of intermediate digital outputs corresponding to successively delayed REFERENCE signals defining the multi-phase clock output signals;
a sequential phase-frequency detector circuit using precharged logic and having a first input connected to the REFERENCE signal and a second input connected to the fully delayed delay line output signal, the phase-frequency detector providing an UP digital control signal and a DOWN digital control signal, the phase-frequency detector circuit being configured to assert the UP signal at a rising edge of the REFERENCE signal, independent of the level of the fully delayed delay line output signal, and including a pulse-generator connected to reset the UP output, and triggered on a rising edge of the fully delayed delay line output signal, and independent of the level of the REFERENCE signal;
a charge-pump circuit connected to receive the UP and DOWN control signals and to control a current in response to the control signals and for coupling the controlled current to an output line;
and
a filter circuit including a capacitor connected to receive the controlled current for providing a filtered control voltage to the analog control voltage input line of the voltage-controlled delay line,
whereby the phase-frequency detector operates to adjust the full delay to correspond to the duration of one cycle of the REFERENCE signal and the intermediate delay line outputs provide successively delayed clock output signals locked to the frequency and phase of the REFERENCE signal.

3 more elements

Dependencies are inferred from the claim text.

Dynamic phase-frequency detector circuit

Life of this patent

Dynamic phase-frequency detector circuit

Life of this patent

Abstract

Claims19