Semiconductor integrated circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsToyoki Takemoto, Haruyasu Yamada, Tsutomu Fujita, Tadao Komeda
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Abstract
In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
Claims4
A method of fabricating a semiconductor integrated circuit, comprising the steps of:
- (a) forming an n-type semiconductor layer on an upper surface of a p-type semiconductor substrate, said n-type semiconductor layer including an n-type first region and an n-type second region;
- (b) forming a p.sup.- -type third region in said n-type second region from an upper surface of said n-type second region;
- (c) simultaneously forming a p.sup.+ -type fourth region and a p.sup.+ -type fifth region in said n-type first region and said p.sup.- -type third region as upper surfaces of said n-type first region and said p.sup.- -type third region, respectively;
- and
- (d) simultaneously forming an n.sup.+ -type sixth region and an n.sup.+ -type seventh region in said p.sup.+ -type fourth region and said p.sup.+ -type fifth region, respectively, from upper surfaces of said p.sup.+ -type fourth region and said p.sup.+ -type fifth region in a manner such that:
- (i) said n.sup.+ -type seventh region is formed within said p.sup.+ -type fifth region to form a p-n junction which establishes a capacitor, and
- (ii) said n.sup.+ -type sixth region is formed within said p.sup.+ -type fourth region in a way such that said n-type first region, said p.sup.+ -type fourth region, and said n.sup.+ -type sixth region form an npn type vertical bipolar transistor;
- said p.sup.- -type third region forming a guarding region which isolates said p.sup.+ -type fifth region from said n-type second region.
A method of fabricating a semiconductor integrated circuit, comprising the steps of:
- (a) forming an n-type semiconductor layer on an upper surface of a p-type semiconductor substrate, said n-type semiconductor layer including an n-type first region and an n-type second region;
- (b) forming a p.sup.- -type third region in said second region from an upper surface of said second region;
- (c) simultaneously forming a p.sup.+ -type fourth region and a p.sup.+ -type fifth region in said n-type first region and said p.sup.- -type third region, respectively, as upper surfaces of said n-type first region and said p.sup.- -type third region;
- (d) simultaneously forming an n.sup.+ -type sixth region and an n.sup.+ -type seventh region in said p.sup.+ -type fourth region and said p.sup.+ -type fifth region, respectively, from upper surfaces of said p.sup.+ -type fourth region and said p.sup.+ -type fifth region in a manner such that:
- (i) said n.sup.+ -type seventh region is formed within said p.sup.+ -type fifth region,
- (ii) said n.sup.+ -type sixth region is formed within said p.sup.+ -type fourth region, and
- (iii) said n-type first region, said p.sup.+ -type fourth region and said n.sup.+ -type sixth region form an npn type vertical transistor;
- (e) forming an insulation layer on said n.sup.+ -type seventh region;
- and
- (f) simultaneously forming a first pair of electrode contacts and a second electrode contact onto said n.sup.+ -type seventh region and said insulation layer in a manner such that an electrical connection between said first pair of electrode contacts crosses and is isolated from said second electrode contact;
- said p.sup.- -type third region forming a guarding region which isolates said p.sup.+ -type fifth region from said n-type second region.
Dependencies are inferred from the claim text.