Method of fabricating compliant interface for semiconductor chip
AssigneeTessera, Inc.
InventorsZlata Kovac, Craig Mitchell, Thomas H. Distefano, John W. Smith
Life of this patent
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Abstract
A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
Claims48
A method of fabricating a compliant interface for a semiconductor chip, comprising the steps of:
- providing a first support structure having a first surface and a porous resilient layer on the first surface of the first support structure;
- abutting a first surface of a second support structure against the porous layer;
- and
- disposing a first curable liquid within the porous layer after the abutting step.
A method of fabricating a compliant interface for a plurality of semiconductor chips, comprising the steps of:
- providing a support structure having a first and a second surface, the second surface having a plurality of terminals thereon;
- attaching a plurality of compliant pads to the first surface of the support structure, the pads defining channels therebetween;
- providing a plurality of separate semiconductor chips each having a contact bearing surface and contacts on such surface, the chips being disposed in an array so that the contact bearing surfaces face in a common direction and define a first chip surface;
- abutting the first chip surface against the compliant pads;
- electrically connecting each terminal to one contact;
- and
- disposing a liquid between the channels after the abutting step, whereby the semiconductor chips and the support structure define a single assembly.
A method of fabricating a compliant interface for a semiconductor wafer, comprising the steps of:
- providing a support structure having a first and a second surface, the second surface having a plurality of terminals thereon;
- attaching a plurality of compliant pads to the first surface of the support structure, the pads defining channels therebetween;
- abutting a first surface of a wafer having a plurality of integral semiconductor chips each having a plurality of contacts thereon against the compliant pads;
- electrically connecting each contact to one terminal;
- and
- disposing a liquid between the channels after the electrically connecting step.
Dependencies are inferred from the claim text.