Line feed circuit with logic level controlled ringing

Abstract

A line-feed circuit which is controllable by logic level control signals from a local microprocessor. One of the logic level signals is a 20 Hz clock signal with a duty cycle of 20 ms high and 30 ms low. Another is an enable signal that allows the ringing driver either to be turned on (and which places the line-feed circuit into a disconnect or "open interval" state so as not to load the ringing signal) or off in which case the ringing driver is placed into a high impedance state so that it will not load signals appearing on the Ring conductor. This permits the ringing driver to be connected directly to the Ring conductor without the need for a series isolating element such as an electromechanical relay or comparable solid state device. The nature of the ringing driver allows the use of a simple ring trip detector comprised of a voltage comparator and duty cycle detector.

Dependencies are inferred from the claim text.