Programmable computer system element with built-in self test method and apparatus for repair during power-on

A computer system element comprising,

• a VLSI array of cells for storing information in the form of bits, bitlines and wordlines, including a redundant array store area which includes a set of fuse registers for said VLSI array bits, bitlines and wordlines,
• an array built-in, on-chip test system (ABIST) for testing said VLSI array, said ABIST having data input ports, data output ports, and address ports, and including:
• a data control register for generating and applying deterministic data patterns to the data input ports of said VLSI array;
• an address control register for generating addresses for application to said array chip in coordination with said data control register;
• a comparator for comparison of data inputted to said data input ports of said VLSI array from said data control register with data outputted from said data output ports of said VLSI array, said comparator including a failing address function store for retaining failing addresses;
• and
• said ABIST further including a a set of registers which mirrors the redundancy fuse registers of said VLSI array.

A computer system element comprising:

• a VLSI array for storing information having redundant areas, and
• an array built-in, on-chip test system (ABIST) for testing said VLSI array, said ABIST having data input ports, data output ports, and address ports, and including:
• a data control register for generating and applying deterministic data patterns to the data input ports of said VLSI array;
• an address control register for generating addresses for application to said array chip in coordination with said data control register;
• a comparator for comparison of data inputted to said data input ports of said VLSI array from said data control register with data outputted from said data output ports of said VLSI array, said comparator including a failing address function store for retaining failing addresses;
• a memory array for storing a plurality of microcode control vectors, each vector including a data control register field, an address control register field, the microcode pointer control register field and a read/write enable control field;
• a microcode pointer control register and finite state machine for means controlling said address control register, said data control register and said microcode pointer control register in response to said plurality of microcode control vectors and to an overflow feedback state of said data control register and said address control register, and wherein
• said VLSI array includes redundant areas for replacing normal functional areas of the VLSI array with ABIST comparator retained failing addresses indicating a hardware error has been detected on power-on of said computer system element, said redundant areas including a plurality of wordlines and a plurality of spare wordlines that can be used to replace other wordlines of the array, each wordline being driven by a wordline decoder having a plurality of input terminals for receiving signals responsive to an address for determining when a selected wordline is to be selected, can be used to replace other wordlines of the array, each spare wordline being driven by a spare wordline decoder having a plurality of input terminals for receiving signals responsive to an address for determining when a selected spare wordline is to be selected, fuse logic for determining whether or not a spare decoder is needed, and if needed for providing a replace.sub.-- needed signal and the value of a faulty address as a fuse vector, said fuse vector determing which spare wordline is to be selected, said fuse logic being activated upon detection of a faulty address during manufacturing test or during detection of an array error when said array is running in system mode.