Resynchronization circuit for a memory system and method of operating same

A method of resynchronizing a stream of data values comprising the steps of:

• detecting a read command signal which initiates a read operation of a stream of data values from a memory system;
• generating a read enable signal in response to detection of said read command signal;
• writing said stream of data values to a first in, first out (FIFO) memory device in response to said read enable signal, wherein said writing is performed in response to a first clock signal;
• generating an output enable signal with a selectable delay in response to said read enable signal;
• transmitting said output enable signal to said FIFO memory device;
• and
• reading said stream of data values out of said FIFO memory device in response to said output enable signal, wherein said reading is performed in response to a second clock signal, thereby synchronizing the stream of data values out of said FIFO memory device with said second clock signal.

A resynchonization circuit for reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the resynchronization circuit comprising:

• a delay circuit coupled to receive the system clock signal, wherein the delay circuit generates a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, wherein the delay circuit introduces a delay to the first clock signal which is approximately equal to the read access latency of the DRAM;
• a first in, first out (FIFO) memory coupled to the delay circuit and the DRAM, wherein the data values read from the DRAM are written to the FIFO memory in response to the first clock signal, and wherein the data values are read from the FIFO memory in response to the system clock signal;
• and
• a latency control circuit coupled to the FIFO memory, wherein the latency control circuit generates a control signal to enable the data values to be read from the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.

A method of reading data values from a dynamic random access memory (DRAM) in response to a system clock signal and a read enable signal, the DRAM having a read access latency, the method comprising the steps of:

• generating a first clock signal in response to the system clock signal, the first clock signal having no definite phase relationship with the system clock signal, the first clock signal lagging the system clock signal by a delay which is approximately equal to the read access latency of the DRAM;
• writing data values read from the DRAM into a first in, first out (FIFO) memory in response to the first clock signal;
• reading data values from the FIFO memory in response to the system clock signal;
• and
• enabling the data values to be read the FIFO memory only after a latency period has expired, the latency period beginning when the read enable signal is asserted and continuing for at least the read access latency of the DRAM array.