Communication control apparatus between processor systems

A communication Control apparatus comprising:

• a first dual port random access memory (DPR) in which a first port is connected to a first processor system;
• a second DPR in which a first port is connected to a second processor system;
• a first communication controller unit connected to a second port of said first DPR;
• a second communication controller unit connected to a second port of said second DPR;
• a communication channel for coupling said first and second communication controller units to each other,
• wherein said first and second communication controller units communication with each other through said communication channel, and, in response to a data write access to an address of one of said first and second DPRs, said first and second communication controller units updates data only at a corresponding address of the other of said first and second DPRs, in order to keep data in the one DPR consistent with data in the other DPR;
• a first logic unit which is connected between said first processor system and said first port of said first DPR and writes data from said first processor system into a desired address in said first DPR in response to a data writing request from said first processor system and reads out data from said desired address of said first DPR in response to a data reading request from said first processor system and sends said data to said first processor system;
• and
• a second logic unit which is connected between said second processor system and aid first port of said second DPR and writes data from said second processor system into a desired address in said second DPR in response to a data writing request form said second processor system and reads out data from said desired address in said second DPR in response to a data reading request from said second processor and sends said data to said second processor system;
• wherein at least one of said first and second logic units includes means for generating an interruption request to a corresponding processor system connected to said at least one logic unit in response to writing of data into a certain area of a corresponding DPR connected to said corresponding processor system by a corresponding communication controller unit connected to said corresponding DPR,
• wherein said corresponding communication controller receives data from a processor system other than said corresponding processor system together with address information of the data to be written in said corresponding DPR, and
• said interrupt request generating means generates said interrupt request when the writing of the data into the certain area of said corresponding DPR is detected based on said address information.

A communication control apparatus for controlling data communication between a master processor system and a plurality of slave processor systems, in which said communication control apparatus includes a plurality of communication control blocks each corresponding to one of said plurality of slave processor systems, wherein each of said communication control blocks comprises:

• a master side dual port random access memory (DPR) in which a first port is connected to said master processor system;
• a slave side DPR in which a first port is connected to a corresponding slave processor system;
• a master side communication controller unit connected to a second port of said master side DPR;
• a slave side communication controller unit connected to a second port of said slave side DPR;
• a communication channel for coupling said master side communication controller unit and said slave side communication controller unit to each other,
• wherein said communication controller units on the master side and slave side communicate with each other through said communication channel, and, in response to a data write access to an address of one of said master and slave side DPRs, said master and slave side communication controller units updates data only at a corresponding address of the other of said master and slave DPRs, in order to keep data in the one DPR consistent with data in the other DPR;
• a master side logic unit which is connected between said master processor system and said first port of said master side DPR and writes data from said master processor system into a desired address in said master side DPR in response to a data writing request from said master processor system and reads out data from said desired address in said master side DPR in response to a data reading request from said master processor system and transfers said data to said master processor system;
• a slave side logic unit which is connected between said corresponding slave processor system and said first port of said slave side DPR and writes data from said corresponding slave processor system into a desired address in said slave side DPR in response to a data writing request from said corresponding slave processor system and reads out data from said desired address in said slave side DPR in response to a data reading request from said corresponding slave processor system and transfers said data to said corresponding slave processor system
• a master arbiter connected to said master logic unit, said master communication controller and said master DPR, for automatically performing arbitration of accesses to said master DPR from said master and slave processor systems;
• and
• a slave arbiter connected to said slave logic unit, said slave communication controller and said slave DPR for automatically performing arbitration of accesses to said slave DPR from said master and slave processor systems.

A communication control apparatus for controlling data communication between a master processor system and a plurality of slave processor systems, in which said communication control apparatus includes a plurality of communication control blocks each corresponding to one of said plurality of slave processor systems, wherein each of said communication control blocks comprises:

• a master side dual port random access memory (DPR) in which a first port is connected to said master processor system;
• a slave side DPR in which a first port is connected to a corresponding slave processor system;
• a master side communication controller unit connected to a second port of said master side DPR;
• a slave side communication controller unit connected to a second port of said slave side DPR;
• and
• a communication channel for coupling said master side communication controller unit and said slave side communication controller unit to each other,
• wherein said communication controller units on the master side and slave side communicate with each other through said communication channel, and, in response to a data write access to an address of one of said master and slave side DPRs, said master and slave side communication controller units updates data only at a corresponding address of the other of said master and slave DPRs, in order to keep data in the one DPR consistent with data in the other DPR,
• a master side logic unit which is connected between said master processor system and said first port of said master side DPR and writes data from said master processor system into a desired address in said master side DPR in response to a data writing request from said master processor system and reads out data from said desired address in said master side DPR in response to a data reading request from said master processor system and transfers said data to said master processor system;
• and
• a slave side logic unit which is connected between said corresponding slave processor system and said first port of said slave side DPR and writes data from said corresponding slave processor system into a desired address in said slave side DPR in response to a data writing request from said corresponding slave processor system and reads out data from said desired addressed said slave side DPR in response to a data reading request from said corresponding slave processor system and transfers said data to said corresponding slave processor system,
• wherein in each of said communication control blocks, at least one of said logic units on the master side and slave side includes means for generating an interruption request to a corresponding processor system connected to said at least one logic unit in response to writing of data into a certain area of a corresponding DPR connected to said corresponding processor system by a corresponding communication controller unit connected to said corresponding DPR,
• wherein said corresponding communication controller receives data from a processor system other than said corresponding processor system together with address information of the data to be written in said corresponding DPR, and
• said interrupt request generating means generates said interrupt request when the writing of the data into the certain area of said corresponding DPR is detected on the basis of said address information.

A communication control apparatus comprising:

• a dual port random access memory (DPR) in which a first port is connected to a first processor system;
• a first communication controller unit connected to a second port of said DPR;
• a second communication controller unit connected to a second processor system;
• a communication channel to couple said first and second communication controller units to each other,
• wherein said first and second communication controller units communicate with each other through said communication channel, and said second processor system accesses said DPR by transmitting information containing an address of an area of said DPR to be accessed from said second communication controller unit to said first communication controller unit through said communication channel;
• and
• a logic unit which is connected between said first processor system and said first port of said DPR and writes data from said first processor system into a desired address in said DPR in response to a data writing request from said first processor system and reads out data from said desired address in said DPR in response to a data reading request from said first processor system and transfers said data to said first processor system,
• an arbiter connected to said logic unit, said first communication controller and said DPR, for automatically performing arbitration of accesses to said DPR from said first and second processor systems.

A communication control apparatus comprising:

• a dual port random access memory (DPR) in which a first port is connected to a first processor system;
• first communication controller unit connected to a second port of said DPR;
• a second communication controller unit connected to a second processor system;
• a communication channel to couple said first and second communication controller units to each other,
• wherein said first and second communication controller units communicate with each other through said communication channel, and said second processor system accesses said DPR by transmitting information containing an address of an area of said DPR to be accessed from said second communication controller unit to said first communication controller unit through said communication channel;
• and
• a logic unit which is connected between said first processor system and said first port of said DPR and writes data from said first processor system into a desired address in said DPR in response to a data writing request from said first processor system and reads out data from said desired address in said DPR in response to a data reading request from said first processor system and transfers said data to said first processor system,
• wherein said logic unit includes means for generating an interruption request to said first processor system in response to writing of data into a certain area in said DPR by said first communication controller unit;
• wherein said first communication controller receives data from a processor system other than said first processor system together with address information of the data to be written in said DPR, and
• said interrupt request generating means generates said interrupt request when the writing of the data into the certain area of said DPR is detected based on said address information.

A communication protocol for supporting a communication from an apparatus A to an apparatus B, in which a communication of an address and data are executed in a following sequence by using three signal lines synchronously with a clock signal which is transmitted from the apparatus A to the apparatus B, comprising the steps of:

• (a) transmitting a control code of total three bits from the apparatus A to the apparatus B, said three bits comprising an MREQN bit (1 bit) indicative of whether a communicating direction is either from the apparatus A to the apparatus B or from the apparatus B to the apparatus A, and a parity code (2 bits) for said address, said data, said MREQN and an MA16N bit (a bit) indicative of whether a number of bits of data to be transmitted is equal to 16 or 8;
• (b) transmitting total 9 bits from the apparatus A to the apparatus B, said 9 bits consisting of 8 bits of said address and the MA16N bit indicating whether the data to be transmitted is either 16 bits or 8 bits, said 9 bits being transmitted three bits at a time three times,
• (c1) wherein said MA16N bit in said step (b) indicates that 8-bit data is transmitted;
• transmitting total nine bits from the apparatus A to the apparatus B, said nine bits consisting of the 8 bit data and one parity bit for the 8 bit data, said address and said MA16N, said nine bits being transmitted three bits at a time three times,
• (c2) wherein said MA16N bit in said step (b) indicates that 16-bit data is transmitted;
• transmitting total 18 bits from the apparatus A to the apparatus B, said 18 bits consisting of the 16 bit data, one parity bit for lower 8 bits of the 16 bit data, said address and said MA16N, and one parity bit for upper 8 bits of the 16 bit data three bits at a time six times;
• and
• (d) producing parity information by said apparatus B on a basis of information as to the address the data received by the apparatus B, and transmitting the parity information from the apparatus B to the apparatus A, said parity information being compared with information on the apparatus A, thereby checking a transfer error by the apparatus A, and when no error is detected, the transfer operation being finished, and when there is an error, the transfer operation being again executed;
• and
• automatically performing arbitration of transmission between said apparatus A and said apparatus B so that transmission from only one of said apparatus A and apparatus B is conducted.

A communication protocol for supporting a communication from an apparatus B to an apparatus A, in which an address and data are communicated in the following steps by using three signal lines synchronously with a clock signal which is transmitted from the apparatus A to the apparatus B, comprising the steps of:

• (a) transmitting from the apparatus B to the apparatus A an SREQN signal indicative of a transmission request from the apparatus B to the apparatus A;
• (b) after said transmission request was accepted by the apparatus A, transmitting a control code of total three bits from the apparatus A to the apparatus B, said three bits consisting of an MREQN bit (1 bit) indicative of whether a communicating direction is either from the apparatus A to the apparatus B or from the apparatus B to the apparatus A, and a parity code (2 bits) for said MREQN, an MA16N bit indicating whether transmission data is of 16 bits or 8 bits, said address and said data;
• (c) transmitting total nine bits from the apparatus B to the apparatus A, said nine bits consisting of eight bits for the address and one MA16N bit indicating whether transmission data is of 16 bits or 8 bits, said nine bits being transmitted three bits at a time three times;
• (d1) wherein said MA16N bit in said step (c) indicates transmission of the 8-bit data;
• transmitting total nine bits from the apparatus B to the apparatus A, said nine bits consisting of the 8 bit data and one parity bit for the 8 bit data, the address and the MA16N, said nine bits being transmitted three bits at a time three times;
• (d2) wherein said MA16N bit in said step (c) indicates transmission of the 16-bit data;
• transmitting total 18 bits from the apparatus B to the apparatus A, said 18 bits consisting of the 16 bit data, one parity bit for lower eight bits of the 16 bit data, the address and the MA16N, and one parity bit for upper eight bits of the 16 bit data, said 18 bits being transmitted three bits at a time six times;
• and
• (e) producing parity information by the apparatus A on a basis of information as to the address and the data received by the apparatus A, and transmitting the parity information from the apparatus A to the apparatus B, said parity information being compared with information on the apparatus B, thereby checking a transfer error by the apparatus B, and when no error exists, the transfer operation being finished, and when there is an error, the transfer operation being again executed;
• automatically performing arbitration of transmission reguests from said apparatus A and said apparatus B so that transmission from only one of said apparatus A and apparatus B is conducted.