Control circuit and method for controlling a data line switching circuit in a semiconductor memory device

Abstract

The present invention relates to a control circuit and method for controlling a data line switching circuit in a semiconductor memory device having a memory cell array, a row decoder for designating a row of a memory cell, a column decoder for designating a column thereof, a bit line sense amplifier which senses a signal of a bit line and amplifies it, and a column selection gate circuit which comprises a plurality of MOS transistors and selectively applies output signals of the bit line sense amplifier to input/output lines via a MOS transistor gated by an output signal of the column decoder among the plurality of MOS transistors. The device includes: an input/output sense amplifier for sensing read data and amplifying it to thereby transmit amplified data to a data line; an address transition detector for detecting a transition of a column address to thereby generate an address transition signal; a data line switching circuit for selecting data amplified through the input/output sense amplifier and transmitting selected data; a first delay circuit for time-delaying a column address strobe signal; a second delay circuit for time-delaying the address transition signal; and a control circuit for controlling the data line switching circuit with a signal obtained by logically combining output signals of the first delay circuit and the second delay circuit.

Dependencies are inferred from the claim text.