Semiconductor memory device with reduced read time and power consumption

A semiconductor memory device comprising:

• at least one memory array which has memory cells, word lines being driven by a row decoder and data from for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;
• a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node;
• a plurality of switching array blocks corresponding to said plurality of sense amplifier blocks, said plurality of switching array blocks each having a plurality of switching elements which connect a pair of bit lines to said first node and to said second node of each of said plurality of sense amplifiers when data is to be read or written;
• and
• a control circuit for independently controlling each of said plurality of sense amplifier blocks and said corresponding plurality of said switching blocks to independently read out data from said memory cells in said memory array.

A semiconductor memory device comprising:

• at least one memory array which has memory cells, word lines being driven by a row decoder and bit lines for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;
• a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node, with at least said first data node of each of said plurality of sense amplifier blocks being selectively connected to at least one of said bit lines in said memory array when data is to be read or written;
• a plurality of register blocks corresponding to said plurality of sense amplifier blocks, each of said plurality of register blocks including a plurality of registers receiving and storing data amplified by said plurality of sense amplifiers;
• and
• a control circuit for independently controlling each of said plurality of sense amplifier blocks and said plurality of register blocks to independently read out data from each of said plurality of register blocks.

A semiconductor memory device comprising:

• at least one memory array which has memory cells, word lines being driven by a row decoder and bit lines for reading data from said memory cells, said memory cells being provided at intersections of said bit lines and said word lines;
• a plurality of sense amplifiers provided for said memory array to read out data from said memory cells in said memory array, said plurality of sense amplifiers forming subsets of plural sense amplifier blocks with all of the sense amplifiers in a sense amplifier block being connected between a first data node and a second data node so as to amplify a signal difference between the first data node and the second data node;
• a plurality of register blocks corresponding to said plurality of sense amplifier blocks, each of said plurality of register blocks including a plurality of registers receiving and storing data amplified by said plurality of sense amplifiers;
• a plurality of switching array blocks corresponding to said plurality of sense amplifier blocks, said plurality of switching array blocks each having a plurality of switching elements which selectively connect a pair of bit lines to said first node and said second node of each of said plurality of said sense amplifiers when data is read or written;
• and
• a control circuit for independently controlling each of said plurality of sense amplifier blocks, said plurality of switching array blocks, and said plurality of register blocks so as to independently read out data from each of said plurality of register blocks.