Method and apparatus for reducing clock-data skew by clock shifting

A method for compensating for propagation delays in a data path, said method comprising the steps of:

• passing a data signal through a data path comprising at least one logic gate, said data path introducing propagation delay onto said data signal, said data signal having an associated clock signal;
• delay shifting said clock signal with a delay circuit to produce a delayed clock signal, said delayed clock signal delayed by a delay time approximately equal to said propagation delay;
• and
• sampling said data signal, said data signal sampled with said delayed clock signal.

An electrical circuit, said electrical circuit comprising the elements of:

• a data input;
• a clock input for receiving a clock signal;
• a data path circuit coupled to said data input, said data path generating a data output, said data path circuit introducing propagation delay;
• a sampling circuit, said sampling circuit sampling said data output;
• and
• a clock shifter circuit coupled to said clock input, said clock shifter circuit introducing a delay time approximately equal to said propagation delay into said clock signal to produce a delayed clock signal, said delayed clock signal driving said sampling circuit.