Method and apparatus for verifying asynchronous circuits using static timing analysis and dynamic functional simulation

In a computer system having a processor coupled to a bus and a memory device coupled to said bus, a computer implemented method for verifying timing behavior of an integrated circuit design having a synchronous region and an asynchronous region, said method comprising the computer implemented steps of:

• analyzing said integrated circuit design using a static timing analyzer to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region;
• simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design using a functional simulator to automatically generate a set of asynchronous test vectors and a set of expected results;
• simulating a response of said design description of said asynchronous region to said set of asynchronous test vectors with said set of signal arrival times applied at said input ports of said design description of said asynchronous region using a full-timing gate-level simulator and generating a set of full timing results therefrom;
• and
• verifying said set of full timing results against said set of expected results.

A computer system having a processor coupled to a bus, a memory device coupled to said bus and apparatus for verifying an integrated circuit design having a synchronous region and an asynchronous region, said apparatus further comprising:

• a static timing analyzer for analyzing said integrated circuit design to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region;
• a functional simulator coupled to receive information from said static timing analyzer, said functional simulator for simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design, wherein said functional simulator automatically generates a set of asynchronous test vectors for application to said asynchronous region and a set of expected results;
• a full timing gate level simulator coupled to receive information from said static timing analyzer and from said functional simulator, said full timing gate level simulator for simulating a response of said design description of said asynchronous region to application of said set of asynchronous test vectors with said set of signal arrival times to said input ports of said asynchronous region, said full timing gate level simulator also for generating a set of full timing results therefrom;
• and
• verification logic for verifying said set of full timing results against said set of expected results.