Prepaging during PCI master initiated wait cycles

A method for optimizing the transfer of data between system memory and a PCI Master device, wherein said PCI Master connects to a PCI bridge through a PCI bus, and the PCI bridge resides on a CPU local bus, and the system memory connects to a memory controller through a memory bus, said memory controller also residing on the CPU local bus, comprising the steps of:

• (a) asserting ownership of the PCI bus by the PCI Master;
• (b) driving an address signal on the PCI bus by the PCI Master;
• (c) generating an address strobe signal on the CPU local bus by the PCI bridge and driving said address signal on the CPU local bus;
• (d) generating a memory wait signal by the PCI bridge to indicate the inability of the PCI Master to immediately complete a data phase of a transaction;
• (e) providing said memory wait signal to said memory controller;
• (f) decoding the address signal by the memory controller;
• (g) opening an appropriate page in the system memory by said memory controller while said memory wait signal is asserted and before said PCI Master is ready to complete the data transaction;
• (h) deasserting the wait signal in response to an indication that the PCI Master is ready to complete the data phase;
• and
• (h) completing the data transaction by the memory controller.

A method for optimizing the transfer of data between system memory and a PCI Master device during a write cycle, wherein said PCI Master connects to a PCI bridge through a PCI bus, and the PCI bridge resides on a CPU local bus, and the system memory connects to a memory controller through a memory bus, said memory controller also residing on the CPU local bus, comprising the steps of:

• (a) the PCI Master gaining ownership of the PCI bus;
• (b) the PCI Master transmitting a burst cycle on the PCI bus;
• (c) said PCI bridge receiving a first address signal and a first data signal from said burst cycle and gaining ownership of said CPU local bus;
• (d) said PCI bridge transmitting said first address signal and said first data signal on said CPU local bus;
• (e) said memory controller writing said first data signal to an address in said system memory corresponding to the first address signal and issuing a memory ready signal to said PCI bridge;
• (f) said PCI bridge issuing a target ready signal to said PCI Master in response to said ready signal from said memory controller;
• (g) said PCI bridge, in the absence of an initiator ready signal from said PCI Master, generating a memory wait signal to the memory controller and providing a second address signal to said memory controller;
• (h) said system memory controller decoding the second address signal to generate a row address and a column address;
• and
• (i) said system memory controller drying the row address of said second address signal to said system memory and asserting a row address strobe (RAS) signal to said system memory to open an appropriate page in said system memory while said memory wait signal is asserted and before said PCI Master is ready to transmit a second data signal on said PCI bus.

A method for optimizing the transfer of data between system memory and a PCI Master device during a read cycle, wherein said PCI Master connects to a PCI bridge through a PCI bus, and the PCI bridge resides on a CPU local bus, and the system memory connects to a memory controller through a memory bus, said memory controller also residing on the CPU local bus, comprising the steps of:

• (a) the PCI Master gaining ownership of the PCI bus;
• (b) the PCI Master transmitting on the PCI bus a first address signal in said system memory to he read;
• (c) said PCI bridge receiving said first address signal and gaining ownership of said CPU local bus;
• (d) said PCI bridge transmitting said first address signal on said CPU local bus;
• (e) said memory controller receiving said first address signal and reading a first data signal in said system memory corresponding to the first address signal and driving said first data signal on said local bus and issuing a memory ready signal to said PCI bridge;
• (f) said PCI bridge issuing a target ready signal to said PCI Master in response to said memory ready signal from said memory controller;
• (g) said PCI bridge, in the absence of an initiator ready signal from said PCI Master, generating a memory wait signal to the memory controller and providing a second address signal to said memory controller.
• (h) said memory controller decoding the second address signal to generate a row address and a column address;
• and
• (i) said memory controller driving the row address of said second address signal to said system memory and asserting a row address strobe (RAS) signal to said system memory to open an appropriate page in memory while said memory wait signal is asserted and before said PCI Master is ready to receive a second data signal.

A system for optimizing memory access times in a computer, comprising:

• a system memory for storing and accessing data;
• a memory controller unit connected to said system memory for controlling accesses to said system memory;
• a PCI bridge connected to said memory controller unit through a CPU local bus;
• a peripheral PCI Master device connected to said PCI bridge through a PCI bus, wherein said PCI Master device asserts ownership of the PCI bus to complete data transactions to the system memory and wherein said PCI bridge asserts ownership of the CPU local bus when the PCI Master asserts ownership of the PCI bus;
• and
• a CPU core connected to said CPU local bus;
• wherein said PCI bridge asserts a memory wait signal to the memory controller and at substantially the same time drives an address in said system memory corresponding to the next data transaction on the CPU local bus to the memory controller unit when the PCI Master device delays in completing a data transfer;
• wherein said memory controller opens an appropriate page in said system memory while said memory wait signal is asserted and while said PCI Master delays in completing the data transfer.