US 5,646,901 A · CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

Abstract

An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.

Claims13

Dependent claims

A CMOS memory cell comprising:

a common floating gate;
a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;
an output node;
an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;
a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;
and
a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.

4 more elements

A method of programming a first CMOS memory cell including a common floating gate;

a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate;
an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel;
and a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein programming results in electrons being added to the common floating gate, programming comprising the steps of:
applying a first voltage difference between the ACG node and the WCL node so that electrons transfer from the source of the NMOS transistor to the common floating gate;
and
applying a second voltage difference, concurrent with application of the first voltage difference, between the ACG node and the WCH node so that substantially no tunneling of electrons occurs from the source of the PMOS transistor to the common floating gate.

3 more elements

Dependencies are inferred from the claim text.

CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

Life of this patent

CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors

Life of this patent

Abstract

Claims13