US 5,646,886 AGranted

Flash memory having segmented array for improved operation

AssigneeNational Semiconductor Corporation

InventorDhaval J. Brahmbhatt

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Abstract

The drain bit line capacitance of a segmented alternate-metal virtual-ground (AMG) flash memory array is reduced by connecting the virtual or noncontinuous bit lines of the array to a drain voltage via select transistors that are not connected to the continuous bit lines that extend through each of the segments of the array.

Claims20

Dependent claims

A flash memory system comprising:

a plurality of memory segments, each memory segment comprising:
a plurality of source bit lines;
a plurality of drain bit lines arranged so that one drain bit line is formed between each adjacent pair of source bit lines;
a plurality of flash memory cells arranged in rows and columns so that in each row of memory cells one cell is formed between each adjacent pair of source and drain bit lines, each of the cells having a source connected to one of the source bit lines, a drain connected to one of the drain bit lines, a channel disposed intermediate the source and drain so as to create a source-channel junction and a drain-channel junction, a floating gate disposed over and insulated from the channel and a control gate disposed over and insulated from the floating gate, the control gate being connected to one of a plurality of word lines;
a plurality of intermediate drain bit lines electrically isolated from the source bit lines;
a plurality of select transistors formed in a pair of rows so that, in each row of select transistors, one select transistor corresponds with every other column of memory cells, and so that, in the pair of rows, one select transistor corresponds with each column of memory cells, each of the select transistors having a first terminal connected to one of the drain bit lines, a second terminal connected to one of the intermediate drain bit lines, and a gate connected to one of a plurality of word lines;
and
control means for programming, reading and erasing the memory cells, the control means including
program means for programming a selected memory cell by electron injection predominately near a first one of the source-channel junctions and drain-channel junctions,
erase means for erasing the memory cells by cold electron injection predominately near a second one of the source-channel junctions and drain-channel junctions, and
read means for reading a selected cell by application of a first voltage to the drain of the selected cell, the voltage being positive with respect to a voltage on the source of the selected cell.

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Dependencies are inferred from the claim text.

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Abstract

A flash memory system comprising:

a plurality of memory segments, each memory segment comprising:
a plurality of source bit lines;
a plurality of drain bit lines arranged so that one drain bit line is formed between each adjacent pair of source bit lines;
a plurality of flash memory cells arranged in rows and columns so that in each row of memory cells one cell is formed between each adjacent pair of source and drain bit lines, each of the cells having a source connected to one of the source bit lines, a drain connected to one of the drain bit lines, a channel disposed intermediate the source and drain so as to create a source-channel junction and a drain-channel junction, a floating gate disposed over and insulated from the channel and a control gate disposed over and insulated from the floating gate, the control gate being connected to one of a plurality of word lines;
a plurality of intermediate drain bit lines electrically isolated from the source bit lines;
a plurality of select transistors formed in a pair of rows so that, in each row of select transistors, one select transistor corresponds with every other column of memory cells, and so that, in the pair of rows, one select transistor corresponds with each column of memory cells, each of the select transistors having a first terminal connected to one of the drain bit lines, a second terminal connected to one of the intermediate drain bit lines, and a gate connected to one of a plurality of word lines;
and
control means for programming, reading and erasing the memory cells, the control means including
program means for programming a selected memory cell by electron injection predominately near a first one of the source-channel junctions and drain-channel junctions,
erase means for erasing the memory cells by cold electron injection predominately near a second one of the source-channel junctions and drain-channel junctions, and
read means for reading a selected cell by application of a first voltage to the drain of the selected cell, the voltage being positive with respect to a voltage on the source of the selected cell.

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