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US 5,646,621 AGranted
Delta-sigma ADC with multi-stage decimation filter and gain compensation filter
AssigneeAdvanced Micro Devices, Inc.
InventorsCarlin Dru Cabler, Alfredo R. Linz
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Abstract
An analog-to-digital conversion circuit is described which includes a front end sigma-delta modulator circuit, a multi-stage digital decimation filter circuit, and a digital compensation filter circuit. An overrange detect circuit is also provided.
Claims22
An analog-to-digital conversion circuit, comprising:
- an oversampling sigma-delta modulator, having a non-unity gain, an input and an output which outputs a multi-bit digital output signal, wherein said input is connected to an analog input signal;
- a multi-stage digital decimation filter, having an input and an output, wherein said multi-stage digital decimation filter input is connected to said output of said sigma-delta modulator, said multi-stage decimation filter having a first stage comprising a sinc.sup.6 integrator-comb filter which decimates by a factor of 16, a second stage comprising a half-band linear phase FIR filter which decimates by a factor of 2, and having a third stage comprising a symmetric, linear phase, FIR low-pass filter which decimates by a factor of 2;
- and a digital compensation filter, said compensation filter having an input and an output, wherein said compensation filter input is connected to said output of said multi-stage digital decimation filter and said output of said compensation filter provides a multi-bit digital output signal, wherein said compensation filter provides attenuation compensation which is the reciprocal of the value of said gain of said sigma-delta modulator.
An analog-to-digital conversion circuit, comprising:
- a 4th order sigma-delta modulator, having a non-unity gain and having an input and an output, wherein said sigma-delta modulator oversamples an analog input signal input to said sigma-delta modulator and converts said analog input signal into a multi-bit digital output signal which is provided at said output of said sigma-delta modulator;
- a multi-stage digital decimation filter, having an input and an output, wherein said multi-stage digital decimation filter input is connected to the output of said sigma-delta modulator circuit;
- and
- a digital compensation filter, having an input and an output, wherein said input of said compensation filter is connected to said output of said multi-stage digital decimation filter, wherein said digital compensation filter provides an attenuation compensation which is the reciprocal value of said gain of said sigma-delta modulator, and wherein a multi-bit digital output signal is provided at said output of said compensation filter.
1 more element
A method of converting an analog signal to a digital signal, comprising the steps of:
- providing a 4th order sigma-delta modulator, having a non-unity gain, and having an input and an output;
- providing an analog input signal to said input of said sigma-delta modulator;
- providing said output of said sigma-delta modulator to an input of a multi-stage digital decimation filter, wherein a multi-bit digital output signal is provided at an output of said multi-stage digital decimation filter and is provided to an input of a digital compensation filter;
- and
- providing attenuation compensation in said compensation filter which is the reciprocal value of said gain of said sigma-delta modulator.
2 more elements
A method of converting an analog signal to a digital signal, comprising the steps of:
- providing an analog input signal to the input of a 4th-order sigma-delta modulator, said modulator having non-unity gain, whereby said modulator oversamples said analog input signal and converts said analog input signal to a multi-bit digital output signal;
- providing said multi-bit digital output signal from said sigma-delta modulator to a first decimator stage of a multi-stage digital decimation filter, wherein said first decimator stage down-samples said multi-bit digital output signal;
- providing a multi-bit first decimator stage output signal to a second decimator stage of said multi-stage digital decimation filter, wherein said second decimator stage down-samples said multi-bit first decimator stage output signal;
- providing a multi-bit second decimator stage output signal to a third decimator stage of said multi-stage digital decimation filter, wherein said third decimator stage down-samples said multi-bit second decimator stage output signal;
- and
- providing a signal output from said third decimator stage to an input of a digital compensation filter, wherein an output of said compensation filter provides a multi-bit digital output signal, wherein said compensation filter provides attenuation compensation which is the reciprocal of the value of said gain of said sigma-delta modulator.
3 more elements
Dependencies are inferred from the claim text.